Intel Intel Gigabit Ethernet Controllers manual PCI-X Status, Usc Scd

PCI Local Bus Interface

4.1.1.4PCI-X Status

31 29

28 26

25 23

22 21

20

19

18

17

16

15

8

7

3

2

0

Res.

Read

Max.

Rd

Cplx

USC

SCD

133

64b

Bus Number

Device

Func.

Size

Split

Byte

Number

Num.

Bits

Read/

Intial

Description

Write

Value

2:0

R

0b

Function Number. This number forms part of the Requester and

Completer IDs for PCI-X transactions.

Device Number. The system assigns a device number (other than 0b) to

7:3

R

1Fh

the Ethernet controller. It forms part of the Requester and Completer IDs

for PCI-X transactions. The Ethernet controller updates this register with

the contents of AD[15:11] on any Type 0 Configuration Write cycle.

Bus Number. This indicates the bus the Ethernet controller is placed on. It

15:8

R

FFh

forms part of the Requester and Completer IDs for PCI-X transactions. The

Ethernet controller updates this register with the contents of AD[7:0] on any

Type 0 Configuration Write cycle.

16

R

1ba

64-bit Device. This indicates the Ethernet controller is a 64-bit device. It

does not indicate the current bus width. It is loaded from the EEPROM

Initialization Control Word 2 (see Section 5.6.12).

133 MHz Capable. A 1b indicates that the Ethernet controller is capable of

17

R

1ba

operating at 133 MHz in PCI-X mode. A 0b indicates 66 MHz capability.

This bit is loaded from the EEPROM Initialization Control Word 2 (see

Section 5.6.12).

read, write 1b

Split Completion Discarded. (Write 1b to clear) This bit is set if the

18

0b

Ethernet controller discards a Split Completion because the requester

to clear

would not accept it.

read, write 1b

Unexpected Split Completion. (Write 1b to clear) This bit indicates

19

0b

whether the Ethernet controller received an unexpected Split Completion

to clear

with its requestor ID.

20

R

0b

Device Complexity. A 0b indicates the Ethernet controller is a simple

device. A 1b indicates that the Ethernet controller is a bridge.

Designed Maximum Memory Read Byte Count. Indicates the maximum

memory read byte count the Ethernet controller is designed to generate.

Register

Maximum Byte Count

0

512

2ba

1

1024

22:21

R

2

2048

3

4096

The value of this register depends on the Max_Read bit in the EEPROM’s

Initialization Control Word 2 (see Section 5.6.12).

• Max_Read = 0b then value = 2 (2 KB)

• Max_Read = 1b then value = 3 (4 KB)

Software Developer’s Manual 81