Intel PCI-X manual Signal Interface, Carrier Sense, Receive Data, Receive Clock

General Initialization and Reset Operation

Signal	Ball	Name and Function
		Carrier Sense.
		TBI: Undefined.
		GMII / MII: This signal indicates traffic activity on the cable, either
CRS	A6	incoming or outgoing. This signal is driven by the PHY. CS is not
		required to transition synchronously with respect to the RX or TX
		clocks. This signal is ignored in full-duplex mode.
		Normal Mode: This signal must be connected to VSS except for test
		mode.
RX_DATA[9] / RX_ER	A9
	D10
RX_DATA[8] / RX_DV		Receive Data.
	B9
RX_DATA[7]		TBI: RX_DATA[9:0] for receive data bus
	C9
RX_DATA[6]		GMII: RX_DATA[7:0] for receive data bus.
	D9
RX_DATA[5]		RX_ER signals a receive error. RX_DV is asserted to indicate data is
RX_DATA[4]	E9	valid on the interface.
RX_DATA[3]	E8	MII: RX_DATA[3:0] for receive data bus.
RX_DATA[2]		RX_ER signals a receive error. RX_DV indicates data is valid on the
	C8
RX_DATA[1]		interface.
	A7
RX_DATA[0]
	B7
		Receive Clock 0.
RBC0 / RX_CLK	C11	TBI: RBC0 is receive clock (62.5 Mbps).
		GMII: RX_CLK is receive clock (125 Mbps).
		MII: RX_CLK is receive clock for 100 Mbps operation (25 Mbps) and
		for 10 Mbps operation (2.5 Mbps).

14.5.1Signal Interface

The external GMII/MII interface is similar in function to the interface used to communicate between the MAC and internal PHY. As with use of the internal PHY, the external GMII/MII interface supports 10/100/1000 Mbps operation, with both half- and full-duplex operation at 10/ 100 Mbps, and full-duplex operation at 1000 Mbps. Unlike the communication path to the internal PHY, the external interface does not provide certain additional control/status interfaces for automatic hardware link setup and/or power-management

Table 14-2lists the signals, functions, and pins used to provide this interface.

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