Register Descriptions

GMII FIFO Register (82541xx and 82547GI/EI Only)

PFIFO (20d; R/W)

Table 13-40. GMII FIFO Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

 

 

 

 

 

 

 

 

An unsigned integer that stipulates the

 

 

 

 

 

number of write clocks to delay the read

 

 

 

 

 

controller after internal GMII’s tx_en is

 

 

 

Buffer Size

3:0

first asserted. This “buffer” protects from

R/W

0101b

0101b

 

 

underflow at the expense of latency.

 

 

 

 

 

The maximum value that can be set is

 

 

 

 

 

13d or Dh.

 

 

 

 

 

 

 

 

 

Enable Speed-Up

 

When set, the PHY advertises higher

 

 

 

 

speed than 10Base-T after reconnect of

 

 

 

Upon Cable

4

R/W

Note 2

Note 2

the cable, even if the software

Reconnect

 

 

 

 

 

advertised only 10Base-T speed.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When set, the PHY optimizes the power

 

 

 

 

 

consumption when the cable is

 

 

 

Power Down On Link

5

disconnected. The PHY gets back to

R/W

Note 1

Note 1

Disconnect

normal operation reconnect of the cable,

 

 

 

 

 

 

supporting Auto-Negotiation and parallel

 

 

 

 

 

detection.

 

 

 

 

 

 

 

 

 

Reserved

7:6

Always read as 0b. Write to 0b for

R/W

00b

00b

normal operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

00b, 01b: Enable the output data bus

 

 

 

 

 

from GMII FIFO to transmitters, drives

 

 

 

 

 

zeros on the output loop-back bus from

 

 

 

 

 

GMII FIFO to external application and to

 

 

 

 

 

DSP RX-FIFOs in test mode.

 

 

 

 

 

10b: Drive zeros on output bus from

 

 

 

FIFO Out Steering

9:8

GMII FIFO to transmitters, enable data

R/W

00b

00b

 

 

on the output loop-back bus from GMII

 

 

 

 

 

FIFO to external application and to DSP

 

 

 

 

 

RX-FIFOs in test mode.

 

 

 

 

 

11b: Enable the output data bus from

 

 

 

 

 

GMII FIFO to both transmitters and

 

 

 

 

 

loop-back bus.

 

 

 

 

 

 

 

 

 

 

 

When set, disables the addition of

 

 

 

Disable Error Out

10

under/overflow errors to the output data

R/W

0b

0b

 

 

stream on internal GMII’s tx_error.

 

 

 

 

 

 

 

 

 

Reserved

13:11

Always read as 0b. Write to 0b for

R/W

0b

0b

normal operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

Status bit set when read clock that is

RO/

 

 

FIFO Overflow

14

faster than internal GMII’s gtx_clk

0b

0b

empties the FIFO mid packet. Increase

LH

 

 

 

 

 

 

the buffer size.

 

 

 

 

 

 

 

 

 

 

 

Status bit set when read clock that is

RO/

 

 

FIFO Underflow

15

slower than internal GMII’s gtx_clk has

0b

0b

allowed the FIFO to fill to capacity mid

LH

 

 

 

 

 

 

packet. Decrease buffer size.

 

 

 

 

 

 

 

 

 

NOTES:

1.The default is determined by EEPROM bit SPD_EN.

2.The default is determined by EEPROM bit ADV10LU.

272

Software Developer’s Manual

Page 286
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Intel PCI-X, Intel Gigabit Ethernet Controllers manual 272