Register Descriptions

Table 13-145. RDFTS Register Bit Description

31

13 12

0

Reserved

FIFO Tail

Field

Bit(s)

Initial

Description

Value

 

 

 

 

 

 

 

FIFO Tail

12:0

0b

A “saved” value of the Receive FIFO Tail pointer.

 

 

 

 

Reserved

31:13

0b

Reads as 0b. Should be written to 0b for future compatibility.

 

 

 

 

13.8.5Receive Data FIFO Packet Count

RDFPC (02430h; R/W)

This register reflects the number of receive packets that are currently in the Receive FIFO. This register is available for diagnostic purposes only, and should not be written during normal operation.

Table 13-146. RDFPC Register Bit Description

31

13 12

0

Reserved

FIFO Tail

Field

Bit(s)

Initial

Description

Value

 

 

 

 

 

 

 

RX FIFO

12:0

0b

The number of received packets currently in the RX FIFO.

Packet Count

 

 

 

 

 

 

 

Reserved

31:13

0b

Reads as 0b. Should be written to 0b for future compatibility.

 

 

 

 

13.8.6Transmit Data FIFO Head Register

TDFH (03410h; R/W)

This register stores the head of the Ethernet controller’s on–chip transmit data FIFO. Since the internal FIFO is organized in units of 64-bit words, this field contains the 64-bit offset of the current Transmit FIFO Head. So a value of “8h” in this register corresponds to an offset of 8 quadwords into the Transmit FIFO space. This register is available for diagnostic purposes only, and should not be written during normal operation.

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Software Developer’s Manual

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Intel Intel Gigabit Ethernet Controllers Receive Data Fifo Packet Count, Transmit Data Fifo Head Register, Tdfh 03410h R/W