Register Descriptions

Table 13-37. PHY Interrupt Status Bit Description

Field

Bit(s)

 

Description

Mode

HW Rst

SW Rst

 

 

 

 

 

 

 

FIFO Over/Underflow

7

1b

= Over/Underflow Error.

RO,

0b

0b

0b

= No FIFO Error.

LH

 

 

 

 

 

 

 

 

 

 

 

False Carrier

8

1b

= False carrier.

RO,

0b

0b

0b

= No false carrier.

LH

 

 

 

 

 

 

 

 

 

 

 

Symbol Error

9

1b

= Symbol error.

RO,

0b

0b

0b

= No symbol error.

LH

 

 

 

 

 

 

 

 

 

 

 

Link Status Changed

10

1b

= Link status changed.

RO,

0b

0b

0b

= Link status not changed.

LH

 

 

 

 

 

 

 

 

 

 

Auto-Negotiation

11

1b = Auto-Negotiation completed.

RO,

0b

0b

Completed

0b = Auto-Negotiation not completed.

LH

 

 

 

 

 

 

 

 

 

 

Page Received

12

1b

= Page received.

RO,

0b

0b

0b

= Page not received.

LH

 

 

 

 

 

 

 

 

 

 

 

Duplex Changed

13

1b

= Duplex changed.

RO,

0b

0b

0b

= Duplex not changed.

LH

 

 

 

 

 

 

 

 

 

 

 

Speed Changed

14

1b

= Speed changed.

RO,

0b

0b

0b

= Speed not changed.

LH

 

 

 

 

 

 

 

 

 

 

 

 

 

1b

= Auto-Negotiation Error.

 

 

 

 

 

0b

= No Auto-Negotiation Error.

 

 

 

Auto-Negotiation

15

An error occurs if MASTER/SLAVE

RO,

0b

0b

does not resolve, parallel detect fault,

Error

LH

 

no common HCD, or link does not

 

 

 

 

 

 

 

 

 

validate after negotiation has

 

 

 

 

 

completed.

 

 

 

 

 

 

 

 

 

 

PHY Link Health Register (82541xx and 82547GI/EI Only)

PLINK (19d; R)

Table 13-38. PHY Link Health Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

 

 

 

 

 

 

Valid Channel A

0

The channel A DSP had converged to

RO

0b

0b

incoming data.

 

 

 

 

 

 

 

 

 

 

 

Valid Channel B

1

The channel B DSP had converged to

RO

0b

0b

incoming data.

 

 

 

 

 

 

 

 

 

 

 

Valid Channel C

2

The channel C DSP had converged to

RO

0b

0b

incoming data.

 

 

 

 

 

 

 

 

 

 

 

Valid Channel D

3

The channel D DSP had converged to

RO

0b

0b

incoming data.

 

 

 

 

 

 

 

 

 

 

 

Auto-Negotiation

4

Auto-Negotiate is actively deciding

RO

0b

0b

Active

HCD.

 

 

 

 

 

 

 

 

 

 

Reserved

5

Always read as 0b.

RO

0b

0b

 

 

 

 

 

 

Software Developer’s Manual

269

Page 283
Image 283
Intel PCI-X, Intel Gigabit Ethernet Controllers manual Hcd