Register Descriptions

13.4.6Extended Device Control Register

CTRL_EXT (00018h, R/W)

This register and the Device Control register (CTRL) controls the major operational modes for the Ethernet controller. CTRL_EXT provides extended control of the Ethernet controller functionality over the Device Control register (CTRL).

Note: See Table 13-12and Table 13-13for the 82544GC/EI.

Table 13-10. CTRL_EXT Register Bit Description

31 - 24

23 - 16 15

0

Reserved

Extended Device Control Bits

Field

Bit(s)

Initial

Description

Value

 

 

 

 

 

 

 

Reserved

1:0

0b

Reserved bits for the 82541xx and 82547GI/EI. Should be written

as 0b to ensure future compatibility.

 

 

 

 

 

 

 

 

 

 

General Purpose Interrupt Enables

 

 

 

These bits determine whether the upper three software definable

GPI_EN

3:0

0b

pins SDP[7:6] and SDP[4] are mapped to the ICR.GPI interrupt

bits. These mappings are enabled only when the SDP[7:6] and

 

 

 

SDP[4] pins are configured as inputs through

 

 

 

CTRL_EXT.SWDPIOHI. Refer to Table 13-11for SDP to ICR.GPI

 

 

 

bit mapping.

 

 

 

 

 

 

 

General Purpose Interrupt Enables for the 82541xx and 82547GI/

 

 

 

EI.

GPI_EN

3:2

0b

These bits determine whether the upper software definable pins

SDP[3:2] are mapped to the ICR.GPI interrupt bits. These

 

 

 

mappings are enabled only when the SDP[3:2] pins are configured

 

 

 

as inputs through CTRL_EXT.SWDPIOHI. Refer to Table 13-11for

 

 

 

SDP to ICR.GPI bit mapping.

 

 

 

 

Reserved

4

0b

Reserved. Formally used as SDP4 pin data value. Reads as 0b.

 

 

 

 

 

 

 

PHY Interrupt Value. When read, returns the current value of the

PHYINT

5

0b

PHY internal interrupt status PHYINT.

 

 

 

Note: This is a reserved bit for the 82541xx and 82547GI/EI.

 

 

 

 

SDP6_DATA

 

 

SDP6[2] Data Value. Used to read (write) value of software-

 

6

0b1

controllable IO pin SDP6[2]. If SDP6[2] is configured as an output

SDP2_DATA

(SDP6[2]_IODIR = 1b), this bit controls the value driven on the pin

(82541xx and

 

 

(initial value EEPROM-configurable). If SDP6[2] is configured as

82547GI/EI)

 

 

an input, reads return the current value of the pin.

 

 

 

 

SDP7_DATA

 

 

SDP7[3] Data Value. Used to read (write) value of software-

 

 

0b1

controllable IO pin SDP7[3]. If SDP7[3] is configured as an output

SDP3_DATA

7

(SDP7[3]_IODIR = 1b), this bit controls the value driven on the pin

(82541xx and

 

 

(initial value EEPROM-configurable). If SDP7[3] is configured as

82547GI/EI)

 

 

an input, reads return the current value of the pin.

 

 

 

 

Reserved

9:8

01b

Reserved

Should be written as 01b to ensure future compatibility.

 

 

 

 

 

 

 

Software Developer’s Manual

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Intel PCI-X manual Extended Device Control Register, Ctrlext 00018h, R/W, Ctrlext Register Bit Description, 23 16