Register Descriptions

Table 13-38. PHY Link Health Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

 

 

 

 

 

 

 

 

Auto-Negotiate Fault: This is the logical

 

 

 

Auto-Negotiation

6

OR of PHY register 1, bit 4, PHY

RO

0b

0b

Fault

register 6, bit 4, and PHY register 10, bit

 

 

 

 

 

 

15.

 

 

 

 

 

 

 

 

 

Reserved

7

Always read as 0b.

RO

0b

0b

 

 

 

 

 

 

 

 

Mode:

 

 

 

Data Err[0]

8

10: 10 Mbps polarity error.

LH

0b

0b

100: Symbol error.

 

 

 

 

 

 

 

1000: Gig idle error.

 

 

 

 

 

 

 

 

 

 

 

Mode:

 

 

 

Data Err[1]

9

10: Reserved.

RO/

0b

0b

100: Scrambler unlocked.

LH

 

 

 

 

 

 

1000: Local receiver not OK.

 

 

 

 

 

 

 

 

 

Count Overflow

10

The idle error counter has overflowed.

RO/

0b

0b

LH

 

 

 

 

 

 

 

 

 

 

 

Gigabit Rem Rcvr

 

Gig has detected a remote receiver

RO/

 

 

11

status error. This is a latched high

0b

0b

NOK

LH

 

version of PHY register 10, bit 12.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gig has resolved to master. This is a

 

 

 

Gigabit Master

12

duplicate of PHY register 10, bit 14.

RO

0b

0b

Resolution

Programmers must read PHY register

 

 

 

 

 

 

10, bit 14 to clear this bit.

 

 

 

 

 

 

 

 

 

 

 

A fault has occurred with the gig master/

 

 

 

 

 

slave resolution process. This is a copy

 

 

 

Gigabit Master Fault

13

of PHY register 10, bit 15.

RO

0b

0b

 

 

Programmers must read PHY register

 

 

 

 

 

10, bit 15 to clear this bit.

 

 

 

 

 

 

 

 

 

 

 

1b indicates that the PHY has detected

 

 

 

 

 

gigabit connection errors that are most

 

 

 

 

 

likely due to a non-IEEE compliant

 

 

 

 

 

scrambler in the link partner.

 

 

 

Gigabit Scrambler

14

0b = Normal scrambled data.

RO

0b

0b

Error

Definition is: If an_enable is true and in

 

 

 

 

 

 

Gigabit mode, on the rising edge of

 

 

 

 

 

internal signal link_fail_inibit

 

 

 

 

 

timer_done, the dsp_lock is true but

 

 

 

 

 

loc_rcvr_OK is false.

 

 

 

 

 

 

 

 

 

SS Downgrade

15

Smart Speed has downgraded the link

RO/

0b

0b

speed from the maximum advertised.

LH

 

 

 

 

 

 

 

 

 

 

270

Software Developer’s Manual

Page 284
Image 284
Intel Intel Gigabit Ethernet Controllers, PCI-X manual Nok