Intel PCI Flow Control Receive Threshold High, Fcrth 02168h R/W, Fcrth Register Bit Description

Register Descriptions

13.4.24Flow Control Receive Threshold High

FCRTH (02168h; R/W)

This register contains the receive threshold used to determine when to send an XOFF packet. It counts in units of bytes. Each time the receive FIFO reaches the fullness indicated by FCRTH, hardware transmits a PAUSE frame if the transmission of flow control frames is enabled (CTRL.TFCE).

Flow control reception/transmission are negotiated capabilities by the Auto-Negotiation process. When the Ethernet controller is manually configured, flow control operation is determined by the CTRL.RFCE & CTRL.TFCE bits.

Table 13-69. FCRTH Register Bit Description

31 30 16 15 3 2 0

XFCE1

Reserved

RTH

0

1.82544GC/EI only.

Field	Bit(s)	Initial	Description
		Value
			Reserved
Reserved	2:0	0b	Should be written with 0 for future compatibility
			Reads as 0
			Receive Threshold High.
RTH	15:3	0b	FIFO high water mark for flow control transmission.
			Each time the receive FIFO reaches the fullness indicated by RTH,
			the Ethernet controller transmits a Pause packet if enabled to do so.
			Reserved
Reserved	31:16	0b	Should be written with 0b for future compatibility.
			Reads as 0b.
			External Flow Control Enabled (82544GC/EI only)
			0b = Disabled.
			1b = Enabled.
			Allows the Ethernet controller to send XOFF and XON frames based
			on external pins XOFF and XON. The transmission of pause frames
XFCE	31	0	must be also enabled through the CTRL.TFCE control bit. When the
			XOFF signal is asserted high, the Ethernet controller transmits a
			single XOFF frame. The assertion of XON (after deassertion of
			XOFF) initiates an XON frame transmission, if enabled by
			FCRTL.XONE. The assertion/deassertion of XON is required
			between assertions of XOFF in order to send another XOFF frame.
			This behavior also provides a built-in hysteresis mechanism.

Software Developer’s Manual 301