Register Descriptions

Table 13-16. PHY Control Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

 

 

 

 

 

 

 

 

1b = Enable Auto-Negotiation Process.

 

 

 

 

 

0b = Disable Auto-Negotiation Process.

 

 

 

 

 

A write to this bit does not take effect

 

 

 

 

 

until a software reset is asserted,

 

 

 

 

 

Restart Auto-Negotiation is asserted, or

 

 

 

 

 

Power Down transitions from power

 

 

 

 

 

down to normal operation.

 

 

 

 

 

When the port is switched from power

 

 

 

 

 

down to normal operation, software

 

 

 

 

 

reset and restart Auto-Negotiation are

 

 

 

 

 

performed even if bits Reset and Restart

 

 

 

 

 

Auto-Negotiation are not set by the

R/W

1b

Update

 

 

programmer.

 

 

 

 

 

If bit 12 is set to 0b and speed is

 

 

 

 

 

manually forced to 1000 Mbps in bits 13

 

 

 

 

 

and 6, then Auto-Negotiation is still

 

 

 

Auto-Negotiation

 

enabled and only 1000BASE-T full

 

 

 

12

duplex is advertised if bit 8 is set to 1b.

 

 

 

Enable

 

 

 

 

1000BASE-T half duplex is advertised if

 

 

 

 

 

 

 

 

 

 

bit 8 is cleared (0b). Duplex settings in

 

 

 

 

 

other registers are ignored. Auto-

 

 

 

 

 

Negotiation is required by IEEE for

 

 

 

 

 

proper operation in 1000BASE-T.

 

 

 

 

 

82544GC/EI only:

R/W

ANEG[3:2]

Update

 

 

Auto-Negotiation enable takes on the

 

ENA_XC

 

 

 

value set by external pins ANEG[3:0] on

 

 

 

 

 

hardware reset only.

 

 

 

 

 

Bit 12: ANEG[3:2] = 11b.

 

 

 

 

 

If MODE[3:0] equals 001xb or 0111b,

 

 

 

 

 

where x equals either 0b or 1b, then the

 

 

 

 

 

ANE bit determines whether

 

 

 

 

 

1000BASE-X Auto-Negotiation is on or

 

 

 

 

 

off. Otherwise ANE determines whether

 

 

 

 

 

10/100/1000BASE-T Auto-Negotiation

 

 

 

 

 

is on or off.

 

 

 

 

 

 

 

 

 

Speed Selection

 

 

R/W

0b

Update

13

See Speed Selection (MSB), bit 6.

 

ANEG[3:1]2

 

(LSB)

 

 

 

MODE[3:0]

 

 

 

 

 

 

 

 

 

 

 

 

Loopback

14

1b = Enable loopback.

R/W

0b

0b

0b = Disable loopback.

 

 

 

 

 

 

 

 

 

 

 

Reset

15

1b = PHY reset.

R/W,

0b

Self

0b = Normal operation.

SC

Clear

 

 

 

 

 

 

 

 

 

1.82541xx and 82547GI/EI only.

2.82544GC/EI only.

Software Developer’s Manual

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Intel Intel Gigabit Ethernet Controllers, PCI-X manual Enaxc, Lsb