Intel PCI-X Transmit Descriptor Command Field Format, Transmit Command TDESC.CMD Layout, Ifcs EOP

Receive and Transmit Description

3.3.3.1Transmit Descriptor Command Field Format

The CMD byte stores the applicable command and has fields shown in Table 3-10.

Table 3-10. Transmit Command (TDESC.CMD) Layout

7 6 5 4 3 2 1 0

IDE

VLE

DEXT

RSV

RPSa

RS

IC

IFCS

EOP

a.82544GC/EI only.

TDESC.CMD	Description
	Interrupt Delay Enable
	When set, activates the transmit interrupt delay timer. The Ethernet controller loads
	a countdown register when it writes back a transmit descriptor that has RS and IDE
	set. The value loaded comes from the IDV field of the Interrupt Delay (TIDV)
IDE (bit 7)	register. When the count reaches 0, a transmit interrupt occurs if transmit descriptor
	write-back interrupts (IMS.TXDW) are enabled. Hardware always loads the transmit
	interrupt counter whenever it processes a descriptor with IDE set even if it is
	already counting down due to a previous descriptor. If hardware encounters a
	descriptor that has RS set, but not IDE, it generates an interrupt immediately after
	writing back the descriptor. The interrupt delay timer is cleared.
	VLAN Packet Enable
	When set, indicates that the packet is a VLAN packet and the Ethernet controller
	should add the VLAN Ethertype and an 802.1q VLAN tag to the packet. The
	Ethertype field comes from the VET register and the VLAN tag comes from the
VLE (bit 6)	special field of the TX descriptor. The hardware inserts the FCS/CRC field in that
	case.
	When cleared, the Ethernet controller sends a generic Ethernet packet. The IFCS
	controls the insertion of the FCS field in that case.
	In order to have this capability CTRL.VME bit should also be set, otherwise VLE
	capability is ignored. VLE is valid only when EOP is set.
DEXT (bit 5)	Extension (0b for legacy mode).
	Should be written with 0b for future compatibility.
	Report Packet Sent
	When set, the 82544GC/EI defers writing the DD bit in the status byte
	(DESC.STATUS) until the packet has been sent, or transmission results in an error
	such as excessive collisions. It is used is cases where the software must know that
RPS	the packet has been sent, and not just loaded to the transmit FIFO. The 82544GC/
	EI might continue to prefetch data from descriptors logically after the one with RPS
RSV (bit 4)
	set, but does not advance the descriptor head pointer or write back any other
	descriptor until it sent the packet with the RPS set. RPS is valid only when EOP is
	set.
	This bit is reserved and should be programmed to 0b for all Ethernet controllers
	except the 82544GC/EI.
	Report Status
	When set, the Ethernet controller needs to report the status information. This ability
RS (bit 3)	may be used by software that does in-memory checks of the transmit descriptors to
	determine which ones are done and packets have been buffered in the transmit
	FIFO. Software does it by looking at the descriptor status byte and checking the
	Descriptor Done (DD) bit.

38 Software Developer’s Manual