Intel Intel Gigabit Ethernet Controllers, PCI-X manual Host Offloading Features

Introduction

•IEEE 802.3x compliant flow control support

—Enables control of the transmission of Pause packets through software or hardware triggering

—Provides indications of receive FIFO status

•State-of-the-art internal transceiver (PHY) with DSP architecture implementation

—Digital adaptive equalization and crosstalk

—Echo and crosstalk cancellation

—Automatic MDI/MDI-X crossover at all speeds and compensation for cable length

—Media Independent Interfaces (MII) IEEE 802.3e for supporting 10/10BASE-T transceivers

•Integrated dual-port solution comprised of two distinct MAC/PHY instances (82546GB/EB)

•Provides on-chip IEEE 802.3z PCS SerDes functionality (82546GB/EB and 82545GM/EM)

1.3.4Host Offloading Features

•Receive and transmit IP and TCP/UDP checksum offloading capabilities

•Transmit TCP Segmentation (operating system support required)

•Packet filtering based on checksum errors

•Support for various address filtering modes:

—16 exact matches (unicast, or multicast)

—4096-bit hash filter for multicast frames

—Promiscuous, unicast and promiscuous multicast transfer modes

•IEEE 802.1q VLAN support1

—Ability to add and strip IEEE 802.1q VLAN tags

—Packet filtering based on VLAN tagging, supporting 4096 tags

•SNMP and RMON statistic counters

•Support for IPv6 including (not applicable to the 82544GC/EI):

—IP/TCP and IP/UDP receive checksum offload

—Wake up filters

—TCP segmentation

1. Not applicable to the 82541ER.

Software Developer’s Manual 3