Intel PCI-X, Intel Gigabit Ethernet Controllers manual 82541xx and 82547GI/EI only, 1b 82541xx

Register Descriptions

13.4.7.1.7Auto-Negotiation Expansion Register ANE (06d; R)

Table 13-25. Auto-Negotiation Expansion Register Bit Description

Field	Bit(s)		Description	Mode	HW Rst	SW Rst
		1b	= Link Partner is Auto-Negotiation
Link Partner Auto-	0	able.		RO	0b	0b
Negotiation Able		0b	= Link Partner is not Auto-
		Negotiation able.
		1b	= A New Page has been received.
		0b	= A New Page has not been
		received.		RO/
Page Received	1	82541xx and 82547GI/EI only:			0b	0b
		If PHY register 16, bit 1 (Alternate NP		LH1
		Feature) is set, the Page Received bit
		also clears when mr_page_rx = false or
		transmit_disable = true.
					0b
Local Next Page Able	2	1b	= Local Device is Next Pageable.	RO	1b (82541xx and
					82547GI/EI)
		1b	= Link Partner is Next Page able.	RO	0b	0b
Link Partner Next		0b	= Link Partner is not Next Page able.
	3
		82544GC/EI only:
Page Able					MODE[3:0]	MODE
		Bit 2 = 1 if MODE[3:0] is not 001xb or
						[3:0]
		0111b.
		1b	= A fault has been detected via the
Parallel Detection	4	Parallel Detection function.		RO/	0b	0b
Fault		0b	= A fault has not been detected via	LH1
		the Parallel Detection function.
		82541xx and 82547GI/EI only:
		This bit indicates the status of the Auto-
		Negotiation variable, base page. If flags
		synchronization with the Auto-
		Negotiation state diagram enabling
Base Page	5	detection of interrupted links. This bit is		RO/	0b	0b
		only used if PHY register 16, bit 1		LH1
		(Alternate NP Feature) is set.
		1b	= base_page = true.
		0b	= base_page = false.
		Note: This is a reserved bit for all
		remaining Ethernet controllers.
Reserved	15:6	0000000000b		RO	Always 000h

1.82541xx and 82547GI/EI only.

NOTE: The ANE Register is not valid until the Auto-Negotiation complete bit in the PHY Status Register indicates completion of the Auto-Negotiation process.

254 Software Developer’s Manual