Intel Intel Gigabit Ethernet Controllers, PCI-X manual Contents

				Contents
Contents
1	Introduction			1
	1.1	Scope		1
	1.2	Overview		1
	1.3	Ethernet Controller Features		2
		1.3.1	PCI Features	2
		1.3.2	CSA Features (82547GI/EI Only)	2
		1.3.3	Network Side Features	2
		1.3.4	Host Offloading Features	3
		1.3.5	Additional Performance Features	4
		1.3.6	Manageability Features (Not Applicable to the 82544GC/EI or
			82541ER)	5
		1.3.7	Additional Ethernet Controller Features	5
		1.3.8	Technology Features	5
	1.4	Conventions		6
		1.4.1	Register and Bit References	6
		1.4.2	Byte and Bit Designations	6
	1.5	Related Documents		6
	1.6	Memory Alignment Terminology		6
2	Architectural Overview			7
	2.1	Introduction		7
	2.2	External Architecture		8
	2.3	Microarchitecture		10
		2.3.1	PCI/PCI-X Core Interface	10
		2.3.2	82547GI/EI CSA Interface	11
		2.3.3	DMA Engine and Data FIFO	11
		2.3.4	10/100/1000 Mb/s Receive and Transmit MAC Blocks	12
		2.3.5	MII/GMII/TBI/Internal SerDes Interface Block	12
		2.3.6	10/100/1000 Ethernet Transceiver (PHY)	13
		2.3.7	EEPROM Interface	13
		2.3.8	FLASH Memory Interface	14
	2.4	DMA Addressing		14
	2.5	Ethernet Addressing		15
	2.6	Interrupts		16
	2.7	Hardware Acceleration Capability		17
		2.7.1	Checksum Offloading	17
		2.7.2	TCP Segmentation	17
	2.8	Buffer and Descriptor Structure		17
3	Receive and Transmit Description			19
	3.1	Introduction		19
	3.2	Packet Reception		19
		3.2.1	Packet Address Filtering	19
		3.2.2	Receive Data Storage	20
		3.2.3	Receive Descriptor Format	20
		3.2.4	Receive Descriptor Fetching	25

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