Intel Intel Gigabit Ethernet Controllers Interrupt Throttling Register1, ITR 000C4h R/W, Interval

Register Descriptions

Field	Bit(s)	Initial	Description
		Value
Reserved	31:17	0b	Reserved
			Reads as 0b.

1.The 82540EP/EM, 82541xx, or 82547GI/EI do not support SerDes functionality.

2.Not applicable to the 82544GC/EI.

Note: The 82547GI/EI signals interrupts over the CSA port, not a dedicated interrupt pin.

13.4.18Interrupt Throttling Register1

ITR (000C4h; R/W)

31 - 16 15 - 0

Reserved

INTERVAL

Field	Bit(s)	Initial	Description
		Value
INTERVAL	15:0	0b	Minimum inter-interrupt interval. The interval is specified in 256 ns
			increments. Setting this bit to 0b disables interrupt throttling logic.
Reserved	31:16	X	Reserved. Should be written with 0b to ensure future compatibility.

Software can use this register to pace (or even out) the delivery of interrupts to the host CPU. This register provides a guaranteed inter-interrupt delay between interrupts asserted by the Ethernet controller, regardless of network traffic conditions. To independently validate configuration settings, software can use the following algorithm to convert the inter-interrupt interval value to the common interrupts/sec performance metric:

interrupts/ sec ond = (256⋅10–9⋅ interval)–1

For example, if the interval is programmed to 500d, the Ethernet controller guarantees the CPU is not interrupted by the Ethernet controller for 128 ∝sec from the last interrupt. The maximum observable interrupt rate from the Ethernet controller must never exceed 7813 interrupts/sec.

Inversely, inter-interrupt interval value can be calculated as:

inter-interrupt interval = (256⋅10–9⋅ interrupts/sec)–1

The optimal performance setting for this register is very system and configuration specific. A initial suggested range is 651-5580 (28Bh - 15CCh).

1.Not applicable to the 82544GC/EI.

Software Developer’s Manual 291