Intel PCI-X, Intel Gigabit Ethernet Controllers Field Bits Description Mode HW Rst SW Rst, Msb

Register Descriptions

13.4.7.1.1PHY Control Register PCTRL (00d; R/W)

Table 13-16. PHY Control Register Bit Description

Field	Bit(s)	Description	Mode	HW Rst	SW Rst
Reserved	5:0	These bits are reserved and should be	RO	Always
		set to 000000b.	RW1	000000b
		Speed Selection is determined by bits 6
		(MSB) and 13 (LSB) as follows.
		11b = Reserved
		10b = 1000 Mbps
		01b = 100 Mbps
		00b = 10 Mbps
		A write to these bits do not take effect
		until a software reset is asserted,
Speed Selection		Restart Auto-Negotiation is asserted, or
	6	Power Down transitions from power	R/W	1b	Update
(MSB)		down to normal operation.
		82544GC/EI only:
		The Speed Selection bits take on the		ANEG[3:2]
		values set by external pins ANEG[3:0]
				MODE[3:0]
		on hardware reset only.
		Bit 6: ANEG[3] ANEG[2] (MODE[3:0]
		is one of xx01b, 1x00b, 001xb, 0111b).
		Bit 13: (ANEG[3:1] = 001b) and
		(MODE[3:0] is not any of xx01b, 1x00b,
		001xb, 0111b).
Collision Test	7	1b = Enable COL signal test.	R/W	0b	0b
		0b = Disable COL signal test.
		1b = Full Duplex.
		0b = Half Duplex.
		82544GC/EI only:		1b
		The Duplex bit takes on the value set by
		external pins ANEG[3:2, 0] on hardware
Duplex Mode	8	reset only.	R/W		Update
		Bit 8: ANEG[3:2,0] = 001 ANEG[3].
				ANEG[3:2,
		A write to this bit does not take effect
		until a software reset is asserted,		0]
		Restart Auto-Negotiation is asserted, or
		Power Down transitions from power
		down to normal power.
		1b = Restart Auto-Negotiation Process.
Restart Auto-		0b = Normal operation.	R/W,		Self
	9	Auto-Negotiation automatically restarts		0b
Negotiation		after hardware or software reset	SC		Clear
		regardless of whether or not the restart
		bit is set.
Isolate	10	1b = Isolate.	R/W	0b	0b
		0b = Normal operation.

Software Developer’s Manual 241