Cypress specifications Operating Modes, CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C

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Operating Modes

CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

Operating Modes

The different modes of operation and EEPROM information are presented in the following sections.

Operational Mode Selection Flow

During the power-up sequence, the AT2LP queries the I2C bus for an EEPROM. The AT2LP then selects a pinout configu- ration as shown below, and checks to see if ARESET# is configured for Board Manufacturing Test Mode.

If no EEPROM is detected, the AT2LP uses the values in the factory-programmable (fused) memory space. See “Fused Memory Data” on page 19 for more information. This

is not a valid mode of operation if no factory programming has been done.

If an EEPROM signature of 0x4D4D is found, the CY7C68300C/CY7C68301C uses the same pinout and EEPROM format as the CY7C68300A (EZ-USB AT2+).

If an EEPROM signature of 0x534B is found, the AT2LP uses the values stored in the EEPROM to configure the USB descriptors for normal operation.

If an EEPROM is detected, but an invalid signature is read, the AT2LP defaults into Board Manufacturing Test Mode.

Figure 10. Operational Mode Selection Flow

Check I2C Bus

Signature 0x534B?

Yes

Set

EZ-USB AT2LP

Pinout

EEPROM

Found?

Yes

No Signature 0x4D4D?

Yes

Set

EZ-USB AT2+ (CY7C68300A)

Pinout

No

Load Fused

Memory Data

(AT2LP Pinout)

VBUS_ATA_ENABLE

No

 

Pin HIGH?

 

Yes

 

ARESET#

No

Pin LOW?

 

Yes

 

DD7 Pin Set

 

HIGH

 

ARESET#

No

 

Pin HIGH?

 

Yes

 

Board Manufacturing

Normal Mass

Test Mode

Storage Mode

Document 001-05809 Rev. *A

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Contents CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C FeaturesBlock Diagram EZ-USB AT2LP USB 2.0 to ATA/ATAPI BridgeIntroduction ApplicationsCY7C68300A Compatibility CY4615C EZ-USB AT2LP Reference Design Kit USB Specification versionCY7C68301C EZ-USB AT2LPCY7C68300C 56-pin SSOPRESET# EZ-USB AT2LP CY7C68300C CY7C68301C 56-pin QFNENABLE DD13CY7C68321C EZ-USB AT2LPCY7C68320C 56-pin SSOPGPIO2 EZ-USB AT2LP CY7C68320C CY7C68321C 56-pin QFNARESET# DD15100-pin TQFP CY7C68320ACY7C68321A page USB D+ signal See “DPLUS, DMINUS” on pageUSB D-signal See “DPLUS, DMINUS” on page PU 10KCY7C68300C/CY7C68301C CY7C68320C/CY7C68321CChip reset See “RESET#” on page VBUS detection See “VBUSATAENABLE” onSCL, SDA “ATAPUEN” on pageDPLUS, DMINUS XTALIN, XTALOUTSYSIRQ USB High-SpeedDRVPWRVLD GPIO PinsATA Interface Pins LOWPWR#ATAPUEN VBUSATAENABLERESET# PWR500#HID Functions for Button Controls Functional OverviewATA Command Block ATACB Field Name Table 6. ATACB Field DescriptionsByte Field Description5-12 Operating Modes Operational Mode Selection FlowFigure 10. Operational Mode Selection Flow Fused Memory Data Bulk-Only Transport Specification . There is a vendor-specificTable 7. Command Block Wrapper Normal Mass Storage ModeMfgCB EEPROM Organization Figure 11. Snapshot of ‘AT2LP Blaster’ Utility“Functional Overview” on page 15 for more detail on how Enable a delay of up to 120 ms at each read of the DRQ bitwhere the device data length does not match the host data length. This allows the CY7C68300C/CY7C68301C to workDetermines if the AT2LP is to do an SRST reset during drive returned on bits 2, 1, and 0 of EP1IN. This bit must be set to CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Configuration does not exist. The USB Mass Storage Class Bulk-OnlyInterface Descriptor USB Bulk Out EndpointUSB Bulk In Endpoint Terminator Number of the channel, must be a zero based value that is Page 29 ofDescriptor-Index 0 LANGID CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Descriptor-Serial Number unique serialLOADCONFIGDATA Label Table 12.EEPROM-related Vendor-specific CommandsREADCONFIGDATA bmRequestTypeDC Characteristics Absolute Maximum RatingsOperating Conditions ATA Timing Characteristics AC Electrical CharacteristicsOrdering Information USB Transceiver CharacteristicsPackage Diagrams Figure 12. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101Package Diagrams continued Figure 13. 56-lead Shrunk Small Outline PackageGeneral PCB Layout Recommendations For USB Mass Storage Designs Figure 14. 56-Lead QFN 8 x 8 mm LF56APage 39 of Quad Flat Package No Leads QFN Package Design Notes Other Design ConsiderationsPCB Material Disclaimers, Trademarks, and Copyrights IDE Removable Media DevicesDevices With Small Buffers Document Number Document History PagedIssue Date ECN NO