Cypress specifications CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C, Features, Block Diagram

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CY7C68300C/CY7C68301C

CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge

Features

Fixed-function mass storage device—requires no firmware

Two power modes: Self-powered and USB bus-powered to enable bus powered CF readers and truly portable USB hard drives

Certified compliant for USB 2.0 (TID# 40490119), the USB Mass Storage Class, and the USB Mass Storage Class Bulk-Only Transport (BOT) Specification

Operates at high-speed (480 Mbps) or full-speed (12 Mbps)

USB

Complies with ATA/ATAPI-6 specification

Supports 48 bit addressing for large hard drives

Supports ATA security features

Supports any ATA command with the ATACB function

Supports mode page 5 for BIOS boot support

Supports ATAPI serial number VPD page retrieval for Digital Rights Management (DRM) compatibility

Supports PIO modes 0, 3, and 4, multiword DMA mode 2, and UDMA modes 2, 3, and 4

Uses one small external serial EEPROM for storage of USB descriptors and device configuration data

ATA interface IRQ signal support

Supports one or two ATA/ATAPI devices

Supports CompactFlash and one ATA/ATAPI device

Supports board-level manufacturing test using the USB I/F

Can place the ATA interface in high impedance (Hi-Z) to allow sharing of the ATA bus with another controller (i.e., an IEEE-1394 to ATA bridge chip or MP3 Decoder)

Low-power 3.3V operation

Fully compatible with native USB mass storage class drivers

Cypress mass storage class drivers available for Windows (98SE, ME, 2000, XP) and Mac OS X operating systems

Features (CY7C68320C/CY7C68321C only)

Supports HID interface or custom GPIOs to enable features such as single button backup, power-off, LED-based notifi- cation, etc.

56-pin QFN and 100-pin TQFP lead-free packages

CY7C68321C is ideal for battery-powered designs

CY7C68320C is ideal for self- and bus-powered designs

Features (CY7C68300C/CY7C68301C only)

Pin-compatible with CY7C68300A (using Backward Compatibility mode)

56-pin SSOP and 56-pin QFN lead-free packages

CY7C68301C is ideal for battery-powered designs

CY7C68300C is ideal for self- and bus-powered designs

Block Diagram

 

 

 

 

 

 

 

 

SCL

I2C Bus Master

 

 

 

 

 

SDA

Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

24

 

PLL

 

 

Misc control signals and GPIO

MHz

 

 

 

 

 

 

 

 

XTAL

 

 

 

 

 

 

 

 

 

 

 

 

ATA 3-state Control

 

 

 

Internal Control Logic

 

 

 

 

 

 

 

Control

ATA Interface

 

 

 

 

 

Control Signals

 

 

 

 

 

 

 

 

 

 

 

 

ATA

 

 

 

 

 

 

Interface

 

 

 

 

 

 

Logic

 

VBUS

USB 2.0

CY Smart USB

 

 

 

USB

D+

4 kByte FIFO

Data

16 Bit ATA Data

Tranceiver

FS/HS Engine

 

D-

 

 

 

 

 

 

 

 

 

Cypress Semiconductor Corporation

198 Champion Court • San Jose, CA 95134-1709

408-943-2600

Document 001-05809 Rev. *A

 

Revised November 30, 2006

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Contents Block Diagram FeaturesCY7C68300C/CY7C68301C CY7C68320C/CY7C68321C EZ-USB AT2LP USB 2.0 to ATA/ATAPI BridgeCY7C68300A Compatibility ApplicationsIntroduction CY4615C EZ-USB AT2LP Reference Design Kit USB Specification versionCY7C68300C EZ-USB AT2LPCY7C68301C 56-pin SSOPENABLE EZ-USB AT2LP CY7C68300C CY7C68301C 56-pin QFNRESET# DD13CY7C68320C EZ-USB AT2LPCY7C68321C 56-pin SSOPARESET# EZ-USB AT2LP CY7C68320C CY7C68321C 56-pin QFNGPIO2 DD15CY7C68320A 100-pin TQFPCY7C68321A USB D-signal See “DPLUS, DMINUS” on page USB D+ signal See “DPLUS, DMINUS” on pagepage PU 10KCY7C68320C/CY7C68321C CY7C68300C/CY7C68301CVBUS detection See “VBUSATAENABLE” on Chip reset See “RESET#” on pageDPLUS, DMINUS “ATAPUEN” on pageSCL, SDA XTALIN, XTALOUTUSB High-Speed SYSIRQATA Interface Pins GPIO PinsDRVPWRVLD LOWPWR#RESET# VBUSATAENABLEATAPUEN PWR500#Functional Overview HID Functions for Button ControlsATA Command Block ATACB Byte Table 6. ATACB Field DescriptionsField Name Field Description5-12 Operational Mode Selection Flow Operating ModesFigure 10. Operational Mode Selection Flow Table 7. Command Block Wrapper Bulk-Only Transport Specification . There is a vendor-specificFused Memory Data Normal Mass Storage ModeMfgCB Figure 11. Snapshot of ‘AT2LP Blaster’ Utility EEPROM Organizationwhere the device data length does not match the host data Enable a delay of up to 120 ms at each read of the DRQ bit“Functional Overview” on page 15 for more detail on how length. This allows the CY7C68300C/CY7C68301C to workDetermines if the AT2LP is to do an SRST reset during drive returned on bits 2, 1, and 0 of EP1IN. This bit must be set to CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C does not exist. The USB Mass Storage Class Bulk-Only ConfigurationUSB Bulk Out Endpoint Interface DescriptorUSB Bulk In Endpoint Terminator Page 29 of Number of the channel, must be a zero based value that isDescriptor-Index 0 LANGID CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C unique serial Descriptor-Serial NumberLOADCONFIGDATA READCONFIGDATA Table 12.EEPROM-related Vendor-specific CommandsLabel bmRequestTypeAbsolute Maximum Ratings DC CharacteristicsOperating Conditions Ordering Information AC Electrical CharacteristicsATA Timing Characteristics USB Transceiver CharacteristicsFigure 12. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101 Package DiagramsFigure 13. 56-lead Shrunk Small Outline Package Package Diagrams continuedFigure 14. 56-Lead QFN 8 x 8 mm LF56A General PCB Layout Recommendations For USB Mass Storage DesignsPage 39 of Other Design Considerations Quad Flat Package No Leads QFN Package Design NotesPCB Material IDE Removable Media Devices Disclaimers, Trademarks, and CopyrightsDevices With Small Buffers Issue Date Document History PagedDocument Number ECN NO