CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C, CfgCB

CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

Fused Memory Data

When no EEPROM is detected at startup, the AT2LP enumerates with the VID/PID/DID values that are stored in the fused memory space. These values can be programmed into the AT2LP during chip manufacturing for high volume applica- tions to avoid the need for an external EEPROM in some designs. Contact your local Cypress Semiconductor sales office for more information on this feature.

If no factory programming has been done, the values returned from the fused memory space would all be 0x00, which is not a valid mode of operation. In this case the chip uses the manufacturing mode and return the default descriptors (VID/PID of 0x4B4/0x6830). An EEPROM must be used with designs that do not use factory-programmed chips in order to identify the device as your company’s product.

Normal Mass Storage Mode

In Normal Mass Storage Mode, the chip behaves as a USB 2.0 to ATA/ATAPI bridge. This includes all typical USB device states (powered, configured, etc.). The USB descriptors are returned according to the values stored in the external EEPROM or fused memory space. A unique serial number is required for Mass Storage Class Bulk-Only Transport compliance, which is one reason why an EEPROM or factory-programmed part is needed.

ATAPI command for EEPROM accesses (CfgCB) and one for board level testing (MfgCB), as described in the following sections.

There is a convenient method available for starting the AT2LP in Board Manufacturing Test Mode to allow reprogramming of EEPROMs without a mass storage device attached. If the ATA Reset (ARESET#) line is LOW on power up, the AT2LP enters Board Manufacturing Test Mode. It is recommended that a 10k resistor be used to pull ARESET# to LOW. An easy way to pull the ARESET# line LOW is to short pins 1 and 3 on the 40-pin ATA connector with a 10k resistor, that ties the ARESET# line to the required pull down on DD7.

CfgCB

The cfg_load and cfg_read vendor-specific commands are passed down through the bulk pipe in the CBWCB portion of the CBW. The format of this CfgCB is shown below. Byte 0 is a vendor-specific command designator whose value is config- urable and set in the configuration data (address 0x04). Byte 1 must be set to 0x26 to identify it as a CfgCB command. Byte2 is reserved and must be set to zero. Byte 3 is used to determine the memory source to write/read. For the AT2LP, this byte must be set to 0x02, indicating the EEPROM is present. Bytes 4 and 5 are used to determine the start address, which must always be 0x0000. Bytes 6 through 15 are reserved and must be set to zero.

Board Manufacturing Test Mode

The data transferred to the EEPROM must be in the format

In Board Manufacturing Test Mode the AT2LP behaves as a

specified in Table 11 of this data sheet. Maximum data transfer

USB 2.0 device but the ATA/ATAPI interface is not fully active.

size is 255 bytes.

This mode must not be used for mass storage operation in a

The data transfer length is determined by the CBW Data

finished design. In this mode, the AT2LP allows for reading

Transfer Length specified in bytes 8 through 11

from and writing to the EEPROM, and for board level testing,

(dCBWDataTransferLength) of the CBW (refer to Table 7).

through vendor specific ATAPI commands utilizing the CBW

The type/direction of the command is determined by the

Command Block as described in the USB Mass Storage Class

direction bit specified in byte 12, bit 7 (bmCBWFlags) of the

Bulk-Only Transport Specification. There is a vendor-specific

CBW (refer to Table 7).

Table 7. Command Block Wrapper

Bits

Offset

0–3

DCBWSignature

4–7

dCBWTag

8–11(08h–0Bh)

dCBWDataTransferLength

12 (0Ch)

bwCBWFLAGS

Dir

Obsolete

Reserved (0)

13 (0Dh)

Reserved (0)

bCBWLUN

14 (0Eh)

Reserved (0)

bCBWCBLength

15–30 (0Fh1Eh)

CBWCB (CfgCB or MfgCB)

Document 001-05809 Rev. *A

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