Cypress CY7C68321C EZ-USB AT2LP CY7C68300C CY7C68301C 56-pin QFN, DD13, DD12, DD11, DD10, Enable

Page 4

DD13

CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

Figure 3. 56-pin QFN Pinout (CY7C68300C/CY7C68301C)

IORDY DMARQ

1

2

GND		VCC

56		55

(NC)
ATAPUEN		GND		DD15		DD14

54		53		52		51

DD13		DD12

50		49

DD11		DD10

48		47

DD9		DD8

46		45

EN)
(ATA
ENABLE
ENABLE
ATA
VBUS		VCC

44		43

42	RESET#
	GND
41	GND

AVCC

XTALOUT

XTALIN

AGND

VCC

DPLUS

DMINUS

GND

VCC

GND

(PU10K) PWR500#

GND

Document 001-05809 Rev. *A

3

4

5

6

7

8

9

10

11

12

13

14

EZ-USB AT2LP

CY7C68300C

CY7C68301C

56-pin QFN

NOTE: Italic labels denote pin functionality during CY7C68300A compatibility mode.

	15		16		17		18		19		20		21		22		23		24		25		26		27		28

	SCL		SDA		VCC		DD0		DD1		DD2		DD3		DD4		DD5		DD6		DD7		GND		VCC		GND

40	ARESET#
	DA2 (VBUS_PWR_VALID)
39
	CS1#
38
	CS0#
37
	DRVPWRVLD (DA2)
36
	DA1
35
	DA0
34
	INTRQ
33
	VCC
32
	DMACK#
31
	DIOR#
30
	DIOW#
29

Page 4 of 42

[+] Feedback

Image 4

Contents Features Block DiagramCY7C68300C/CY7C68301C CY7C68320C/CY7C68321C EZ-USB AT2LP USB 2.0 to ATA/ATAPI BridgeApplications CY7C68300A CompatibilityIntroduction CY4615C EZ-USB AT2LP Reference Design Kit USB Specification versionEZ-USB AT2LP CY7C68300CCY7C68301C 56-pin SSOPEZ-USB AT2LP CY7C68300C CY7C68301C 56-pin QFN ENABLERESET# DD13EZ-USB AT2LP CY7C68320CCY7C68321C 56-pin SSOPEZ-USB AT2LP CY7C68320C CY7C68321C 56-pin QFN ARESET#GPIO2 DD15CY7C68320A 100-pin TQFPCY7C68321A USB D+ signal See “DPLUS, DMINUS” on page USB D-signal See “DPLUS, DMINUS” on pagepage PU 10KCY7C68300C/CY7C68301C CY7C68320C/CY7C68321CChip reset See “RESET#” on page VBUS detection See “VBUSATAENABLE” on“ATAPUEN” on page DPLUS, DMINUSSCL, SDA XTALIN, XTALOUTSYSIRQ USB High-SpeedGPIO Pins ATA Interface PinsDRVPWRVLD LOWPWR#VBUSATAENABLE RESET#ATAPUEN PWR500#Functional Overview HID Functions for Button ControlsATA Command Block ATACB Table 6. ATACB Field Descriptions ByteField Name Field Description5-12 Operational Mode Selection Flow Operating ModesFigure 10. Operational Mode Selection Flow Bulk-Only Transport Specification . There is a vendor-specific Table 7. Command Block WrapperFused Memory Data Normal Mass Storage ModeMfgCB EEPROM Organization Figure 11. Snapshot of ‘AT2LP Blaster’ UtilityEnable a delay of up to 120 ms at each read of the DRQ bit where the device data length does not match the host data“Functional Overview” on page 15 for more detail on how length. This allows the CY7C68300C/CY7C68301C to workDetermines if the AT2LP is to do an SRST reset during drive returned on bits 2, 1, and 0 of EP1IN. This bit must be set to CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Configuration does not exist. The USB Mass Storage Class Bulk-OnlyUSB Bulk Out Endpoint Interface DescriptorUSB Bulk In Endpoint Terminator Number of the channel, must be a zero based value that is Page 29 ofDescriptor-Index 0 LANGID CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Descriptor-Serial Number unique serialLOADCONFIGDATA Table 12.EEPROM-related Vendor-specific Commands READCONFIGDATALabel bmRequestTypeAbsolute Maximum Ratings DC CharacteristicsOperating Conditions AC Electrical Characteristics Ordering InformationATA Timing Characteristics USB Transceiver CharacteristicsPackage Diagrams Figure 12. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101Package Diagrams continued Figure 13. 56-lead Shrunk Small Outline PackageFigure 14. 56-Lead QFN 8 x 8 mm LF56A General PCB Layout Recommendations For USB Mass Storage DesignsPage 39 of Other Design Considerations Quad Flat Package No Leads QFN Package Design NotesPCB Material IDE Removable Media Devices Disclaimers, Trademarks, and CopyrightsDevices With Small Buffers Document History Paged Issue DateDocument Number ECN NO