Cypress CY7C68301C EZ-USB AT2LP CY7C68320C CY7C68321C 56-pin QFN, GPIO2, DD15, DD14, DD13, DD12

Page 6

CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

Figure 5. 56-pin QFN Pinout (CY7C68320C/CY7C68321C)

IORDY 1

DMARQ 2

GND	VCC	GPIO2	GND	DD15	DD14	DD13	DD12

56	55	54	53	52	51	50	49

				ATA ENABLE
DD11	DD10	DD9	DD8	VBUS_	VCC

48	47	46	45	44	43

42	RESET#
	GND
41	GND

AVCC 3

XTALOUT 4

XTALIN 5

AGND 6

VCC 7

DPLUS 8

DMINUS 9

GND 10

VCC 11

GND 12

GPIO1 13

GND 14

Document 001-05809 Rev. *A

EZ-USB AT2LP

CY7C68320C

CY7C68321C

56-pin QFN

15	16	17	18	19	20	21	22		23	24	25	26	27	28

SCL	SDA	VCC	DD0	DD1	DD2	DD3	DD4	DD5		DD6	DD7	GND	VCC	GND

40	ARESET#
	DA2
39
	CS1#
38
	CS0#
37
	GPIO0
36
	DA1
35
	DA0
34
	INTRQ
33
	VCC
32
	DMACK#
31
	DIOR#
30
	DIOW#
29

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Contents CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C FeaturesBlock Diagram EZ-USB AT2LP USB 2.0 to ATA/ATAPI BridgeIntroduction ApplicationsCY7C68300A Compatibility CY4615C EZ-USB AT2LP Reference Design Kit USB Specification versionCY7C68301C EZ-USB AT2LPCY7C68300C 56-pin SSOPRESET# EZ-USB AT2LP CY7C68300C CY7C68301C 56-pin QFNENABLE DD13CY7C68321C EZ-USB AT2LPCY7C68320C 56-pin SSOPGPIO2 EZ-USB AT2LP CY7C68320C CY7C68321C 56-pin QFNARESET# DD15100-pin TQFP CY7C68320ACY7C68321A page USB D+ signal See “DPLUS, DMINUS” on pageUSB D-signal See “DPLUS, DMINUS” on page PU 10KCY7C68300C/CY7C68301C CY7C68320C/CY7C68321CChip reset See “RESET#” on page VBUS detection See “VBUSATAENABLE” onSCL, SDA “ATAPUEN” on pageDPLUS, DMINUS XTALIN, XTALOUTSYSIRQ USB High-SpeedDRVPWRVLD GPIO PinsATA Interface Pins LOWPWR#ATAPUEN VBUSATAENABLERESET# PWR500#HID Functions for Button Controls Functional OverviewATA Command Block ATACB Field Name Table 6. ATACB Field DescriptionsByte Field Description5-12 Operating Modes Operational Mode Selection FlowFigure 10. Operational Mode Selection Flow Fused Memory Data Bulk-Only Transport Specification . There is a vendor-specificTable 7. Command Block Wrapper Normal Mass Storage ModeMfgCB EEPROM Organization Figure 11. Snapshot of ‘AT2LP Blaster’ Utility“Functional Overview” on page 15 for more detail on how Enable a delay of up to 120 ms at each read of the DRQ bitwhere the device data length does not match the host data length. This allows the CY7C68300C/CY7C68301C to workDetermines if the AT2LP is to do an SRST reset during drive returned on bits 2, 1, and 0 of EP1IN. This bit must be set to CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Configuration does not exist. The USB Mass Storage Class Bulk-OnlyInterface Descriptor USB Bulk Out EndpointUSB Bulk In Endpoint Terminator Number of the channel, must be a zero based value that is Page 29 ofDescriptor-Index 0 LANGID CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Descriptor-Serial Number unique serialLOADCONFIGDATA Label Table 12.EEPROM-related Vendor-specific CommandsREADCONFIGDATA bmRequestTypeDC Characteristics Absolute Maximum RatingsOperating Conditions ATA Timing Characteristics AC Electrical CharacteristicsOrdering Information USB Transceiver CharacteristicsPackage Diagrams Figure 12. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101Package Diagrams continued Figure 13. 56-lead Shrunk Small Outline PackageGeneral PCB Layout Recommendations For USB Mass Storage Designs Figure 14. 56-Lead QFN 8 x 8 mm LF56APage 39 of Quad Flat Package No Leads QFN Package Design Notes Other Design ConsiderationsPCB Material Disclaimers, Trademarks, and Copyrights IDE Removable Media DevicesDevices With Small Buffers Document Number Document History PagedIssue Date ECN NO

15	16	17	18	19	20	21	22		23	24	25	26	27	28

SCL	SDA	VCC	DD0	DD1	DD2	DD3	DD4	DD5		DD6	DD7	GND	VCC	GND

15	16	17	18	19	20	21	22		23	24	25	26	27	28

SCL	SDA	VCC	DD0	DD1	DD2	DD3	DD4	DD5		DD6	DD7	GND	VCC	GND

GPIO2

DD15

DD14

EZ-USB AT2LP

ARESET#

CS1#

CS0#

GPIO0

INTRQ

DMACK#

DIOR#

DIOW#

15	16	17	18	19	20	21	22		23	24	25	26	27	28

SCL	SDA	VCC	DD0	DD1	DD2	DD3	DD4	DD5		DD6	DD7	GND	VCC	GND