Cypress specifications CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C

Page 25
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CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

Table 11.Configuration Data Organization (continued)

 

Byte

Configuration

Configuration

Required

Variable

 

Address

Item Name

Item Description

Contents

Contents

 

 

 

 

 

 

 

0x0A

Reserved

Bits 7:6

 

0x00

 

 

 

Reserved. Must be set to zero.

 

 

 

 

GPIO Output Pin State

Bits 5:0

 

 

 

 

 

These bits select the value driven on the GPIO pins that are

 

 

 

 

 

configured as outputs in configuration address 0x09.

 

 

 

 

 

0 = Drive the GPIO pin LOW

 

 

 

 

 

1 = Drive the GPIO pin HIGH

 

 

 

0x0B

LUN0 Identify String

This byte is a pointer to the start of a 24 byte ASCII

 

0x00

 

 

 

(non-Unicode) string in the EEPROM that is used as the

 

 

 

 

 

LUN0 device identifier. This string is used by many operating

 

 

 

 

 

systems as the user-visible name for the drive. If this byte is

 

 

 

 

 

0x00, the Identify Device data from the drive is used instead.

 

 

 

0x0C

LUN1 Identify String

This byte is a pointer to the start of a 24 byte ASCII

 

0x00

 

 

 

(non-Unicode) string in the EEPROM that is used as the

 

 

 

 

 

LUN1 device identifier. This string is used by many operating

 

 

 

 

 

systems as the user-visible name for the drive. If this byte is

 

 

 

 

 

0x00, the Identify Device data from the drive is used instead.

 

 

 

0x0D

Delay After Reset

Number of 20-ms ticks to wait between AT2LP startup or

 

0x00

 

 

 

reset, and the first attempt to access any drives.

 

 

 

0x0E

Reserved

Bits 7:5

 

0x00

 

 

 

Must be set to zero.

 

 

 

 

Bus-Powered Flag

Bit 4

 

 

 

 

 

Enable bus-powered HDD support. This bit enables the use

 

 

 

 

 

of DRVPWRVLD features without reporting the LUN0 device

 

 

 

 

 

as removable media.

 

 

 

 

 

0 = LUN0 is removable media or DRVPWRVLD is disabled

 

 

 

 

 

1 = LUN0 device is bus-powered and non-removable

 

 

 

 

CF UDMA Enable

Bit 3

 

 

 

 

 

Enable UDMA transfers for removable devices. Some CF

 

 

 

 

 

devices interfere with UDMA transfers when more than one

 

 

 

 

 

drive is connected to the ATA bus.

 

 

 

 

 

0 = Do not use UDMA transfers with removable devices

 

 

 

 

 

(UDMA signals are not connected to the CF pins).

 

 

 

 

 

1 = Allow UDMA transfers to be used with removable

 

 

 

 

 

devices (UDMA signals are connected to the CF pins).

 

 

 

 

Fixed Number of Logical

Bits 2:1

 

 

 

 

 

Assume the presence of devices and do not perform a

 

 

 

 

 

search of the ATA bus to discover the number of LUNs.

 

 

 

 

 

00 = Search ATA bus and determine number of LUNs

 

 

 

 

 

01 = Assume only LUN0 present; no ATA bus search

 

 

 

 

 

10 = Assume LUN0 and LUN1 present; no ATA bus search

 

 

 

 

 

11 = Assume LUN0 and LUN1 present; no ATA bus search

 

 

 

 

Search ATA on VBUS

Bit 0

 

 

 

 

 

Search for ATA devices when VBUS returns. If this bit is set,

 

 

 

 

 

the ATA bus is searched for ATA devices every time

 

 

 

 

 

VBUS_ATA_ENABLE is asserted. This feature allows the

 

 

 

 

 

AT2LP to be used in designs where the drive may be physi-

 

 

 

 

 

cally removed (like docking stations or port replicators).

 

 

 

 

 

0 = Search ATA bus on VBUS_ATA_ENABLE assertion

 

 

 

 

 

1 = No ATA bus search on VBUS_ATA_ENABLE assertion

 

 

 

0x0F

Reserved

Must be set to 0x00

0x00

 

 

 

 

 

 

 

 

Device Descriptor

 

 

 

 

0x10

bLength

Length of device descriptor in bytes

0x12

 

 

 

 

 

 

 

 

0x11

bDescriptor Type

Descriptor type.

0x01

 

 

 

 

 

 

 

Document 001-05809 Rev. *A

 

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Contents Block Diagram FeaturesCY7C68300C/CY7C68301C CY7C68320C/CY7C68321C EZ-USB AT2LP USB 2.0 to ATA/ATAPI BridgeCY7C68300A Compatibility ApplicationsIntroduction CY4615C EZ-USB AT2LP Reference Design Kit USB Specification versionCY7C68300C EZ-USB AT2LPCY7C68301C 56-pin SSOPENABLE EZ-USB AT2LP CY7C68300C CY7C68301C 56-pin QFNRESET# DD13CY7C68320C EZ-USB AT2LPCY7C68321C 56-pin SSOPARESET# EZ-USB AT2LP CY7C68320C CY7C68321C 56-pin QFNGPIO2 DD15CY7C68320A 100-pin TQFPCY7C68321A USB D-signal See “DPLUS, DMINUS” on page USB D+ signal See “DPLUS, DMINUS” on pagepage PU 10KCY7C68320C/CY7C68321C CY7C68300C/CY7C68301CVBUS detection See “VBUSATAENABLE” on Chip reset See “RESET#” on pageDPLUS, DMINUS “ATAPUEN” on pageSCL, SDA XTALIN, XTALOUTUSB High-Speed SYSIRQATA Interface Pins GPIO PinsDRVPWRVLD LOWPWR#RESET# VBUSATAENABLEATAPUEN PWR500#Functional Overview HID Functions for Button ControlsATA Command Block ATACB Byte Table 6. ATACB Field DescriptionsField Name Field Description5-12 Operational Mode Selection Flow Operating ModesFigure 10. Operational Mode Selection Flow Table 7. Command Block Wrapper Bulk-Only Transport Specification . There is a vendor-specificFused Memory Data Normal Mass Storage ModeMfgCB Figure 11. Snapshot of ‘AT2LP Blaster’ Utility EEPROM Organizationwhere the device data length does not match the host data Enable a delay of up to 120 ms at each read of the DRQ bit“Functional Overview” on page 15 for more detail on how length. This allows the CY7C68300C/CY7C68301C to workDetermines if the AT2LP is to do an SRST reset during drive returned on bits 2, 1, and 0 of EP1IN. This bit must be set to CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C does not exist. The USB Mass Storage Class Bulk-Only ConfigurationUSB Bulk Out Endpoint Interface DescriptorUSB Bulk In Endpoint Terminator Page 29 of Number of the channel, must be a zero based value that isDescriptor-Index 0 LANGID CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C unique serial Descriptor-Serial NumberLOADCONFIGDATA READCONFIGDATA Table 12.EEPROM-related Vendor-specific CommandsLabel bmRequestTypeAbsolute Maximum Ratings DC CharacteristicsOperating Conditions Ordering Information AC Electrical CharacteristicsATA Timing Characteristics USB Transceiver CharacteristicsFigure 12. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101 Package DiagramsFigure 13. 56-lead Shrunk Small Outline Package Package Diagrams continuedFigure 14. 56-Lead QFN 8 x 8 mm LF56A General PCB Layout Recommendations For USB Mass Storage DesignsPage 39 of Other Design Considerations Quad Flat Package No Leads QFN Package Design NotesPCB Material IDE Removable Media Devices Disclaimers, Trademarks, and CopyrightsDevices With Small Buffers Issue Date Document History PagedDocument Number ECN NO