Cypress Package Diagrams, CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C, + Feedback

Page 37

CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

Package Diagrams

Figure 12. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

16.00±0.20

14.00±0.10

1.40±0.05

100	81
1	80

22.00±0.20

20.00±0.10

0.30±0.08

0.65	12° ±1°
TYP.	(8X)

SEE DETAIL

0.20 MAX.

1.60 MAX.

R 0.08 MIN. 0.20 MAX.

0.25

0° MIN.

SEATING PLANE

STAND-OFF

0.05 MIN.NOTE:

0.15 MAX.

0.10

GAUGE PLANE

0° -7°

0.60±0.15

1.00 REF.

R 0.08 MIN. 0.20 MAX.

0.20 MIN.

DETAIL A

1.JEDEC STD REF MS-026

2.BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3.DIMENSIONS IN MILLIMETERS

51-85050-*B

Document 001-05809 Rev. *A

Page 37 of 42

[+] Feedback

Image 37

Contents Block Diagram FeaturesCY7C68300C/CY7C68301C CY7C68320C/CY7C68321C EZ-USB AT2LP USB 2.0 to ATA/ATAPI BridgeCY7C68300A Compatibility ApplicationsIntroduction CY4615C EZ-USB AT2LP Reference Design Kit USB Specification versionCY7C68300C EZ-USB AT2LPCY7C68301C 56-pin SSOPENABLE EZ-USB AT2LP CY7C68300C CY7C68301C 56-pin QFNRESET# DD13CY7C68320C EZ-USB AT2LPCY7C68321C 56-pin SSOPARESET# EZ-USB AT2LP CY7C68320C CY7C68321C 56-pin QFNGPIO2 DD15CY7C68320A 100-pin TQFPCY7C68321A USB D-signal See “DPLUS, DMINUS” on page USB D+ signal See “DPLUS, DMINUS” on pagepage PU 10KCY7C68320C/CY7C68321C CY7C68300C/CY7C68301CVBUS detection See “VBUSATAENABLE” on Chip reset See “RESET#” on pageDPLUS, DMINUS “ATAPUEN” on pageSCL, SDA XTALIN, XTALOUTUSB High-Speed SYSIRQATA Interface Pins GPIO PinsDRVPWRVLD LOWPWR#RESET# VBUSATAENABLEATAPUEN PWR500#Functional Overview HID Functions for Button ControlsATA Command Block ATACB Byte Table 6. ATACB Field DescriptionsField Name Field Description5-12 Operational Mode Selection Flow Operating ModesFigure 10. Operational Mode Selection Flow Table 7. Command Block Wrapper Bulk-Only Transport Specification . There is a vendor-specificFused Memory Data Normal Mass Storage ModeMfgCB Figure 11. Snapshot of ‘AT2LP Blaster’ Utility EEPROM Organizationwhere the device data length does not match the host data Enable a delay of up to 120 ms at each read of the DRQ bit“Functional Overview” on page 15 for more detail on how length. This allows the CY7C68300C/CY7C68301C to workDetermines if the AT2LP is to do an SRST reset during drive returned on bits 2, 1, and 0 of EP1IN. This bit must be set to CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C does not exist. The USB Mass Storage Class Bulk-Only ConfigurationUSB Bulk Out Endpoint Interface DescriptorUSB Bulk In Endpoint Terminator Page 29 of Number of the channel, must be a zero based value that isDescriptor-Index 0 LANGID CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C unique serial Descriptor-Serial NumberLOADCONFIGDATA READCONFIGDATA Table 12.EEPROM-related Vendor-specific CommandsLabel bmRequestTypeAbsolute Maximum Ratings DC CharacteristicsOperating Conditions Ordering Information AC Electrical CharacteristicsATA Timing Characteristics USB Transceiver CharacteristicsFigure 12. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101 Package DiagramsFigure 13. 56-lead Shrunk Small Outline Package Package Diagrams continuedFigure 14. 56-Lead QFN 8 x 8 mm LF56A General PCB Layout Recommendations For USB Mass Storage DesignsPage 39 of Other Design Considerations Quad Flat Package No Leads QFN Package Design NotesPCB Material IDE Removable Media Devices Disclaimers, Trademarks, and CopyrightsDevices With Small Buffers Issue Date Document History PagedDocument Number ECN NO