Cypress CY7C68300C General PCB Layout Recommendations For USB Mass Storage Designs, Page 39 of

CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

Package Diagrams (continued)

Figure 14. 56-Lead QFN 8 x 8 mm LF56A

DIMENSIONS IN MM[INCHES] MIN.

MAX.

REFERENCE JEDEC MO-220

TOP VIEW

A	7.90[0.311]
	8.10[0.319]
	7.70[0.303]
	7.80[0.307]
	N

1

0.80[0.031]2

DIA.

SIDE VIEW

1.00[0.039] MAX.	0.08[0.003]	C
	0.05[0.002] MAX.
0.80[0.031] MAX.
	0.20[0.008] REF.

BOTTOM VIEW

0.18[0.007]

0.28[0.011]

N		PIN1 ID
		0.20[0.008] R.
	1
	2	0.45[0.018]

7.70[0.303] 7.80[0.307] 7.90[0.311] 8.10[0.319]

0.30[0.012]

0.50[0.020]

E-PAD

(PAD SIZE VARY BY DEVICE TYPE)

6.45[0.254] 6.55[0.258]

OPTION FOR CML - BOTTOM VIEW

	.680
N
1	1.925
2	R.100
	R.600
	R.500
	R.400
	R.300
E-PAD	R.200
	PIN #1 ID
	.000
(PAD SIZE VARY
BY DEVICE TYPE)	.680
	R.400
	R.300
	2.175
	2.275

	0°-12°
.000	.240TYP

R.250

(3X)

R.100

R.200

C

SEATING PLANE

2.125 2.225 2.325

2.375

1.975

2.075

0.50[0.020]

6.45[0.254]

6.55[0.258]

0.24[0.009] (4X) 0.60[0.024]

U-GROOVE DIMENSION

NOTE:

DIMENSIONS ARE SAME WITH STD DWG ON UPPER RIGHT EXCEPT

FOR THE U-GROOVE ON THE PADDLE

51-85144 *F

General PCB Layout Recommendations For USB Mass Storage Designs

The following recommendations must be followed to ensure reliable high-performance operation:

•Use at least a four-layer, impedance controlled board to maintain signal quality.

•Specify specific impedance targets (ask your board vendor what they can achieve).

•Maintain uniform trace widths and trace spacing to control impedance.

•Minimize reflected signals by avoiding using stubs and vias.

•Connect the USB connector shell and signal ground as near to the USB connector as possible.

•Use bypass/flyback capacitors on VBUS near the connector.

•Keep DPLUS and DMINUS trace lengths to within 2 mm of each other in length, with a preferred length of 20–30 mm.

•Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces.

•Do not place vias on the DPLUS or DMINUS trace routing for a more stable design.

•Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm.

•Source for recommendations:

•EZ-USB FX2LP PCB Design Recommendations http://www.cypress.com

•High-speed USB Platform Design Guidelines http://www.usb.org

Document 001-05809 Rev. *A Page 39 of 42

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