Cypress CY7C68320C, CY7C68301C, CY7C68300C EZ-USB AT2LP, CY7C68321C, pin SSOP, + Feedback

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CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

Figure 4. 56-pin SSOP Pinout (CY7C68320C/CY7C68321C)

	DD13		DD12
1	DD13		DD12
	DD14		DD11
2	DD14		DD11
	DD15		DD10
3	DD15		DD10
	GND		DD9
4	GND		DD9
	GPIO2		DD8
5	GPIO2		DD8
	VCC	VBUS_ATA_ENABLE
6	VCC	VBUS_ATA_ENABLE
	GND		VCC
7	GND		VCC
	IORDY		RESET#
8	IORDY		RESET#
	DMARQ		GND
9	DMARQ		GND
	AVCC		ARESET#
10	AVCC		ARESET#
	XTALOUT		DA2
11	XTALOUT		DA2
	XTALIN		CS1#
12	XTALIN		CS1#
	AGND		CS0#
13	AGND		CS0#
	VCC		GPIO0
14	VCC		GPIO0
	DPLUS	EZ-USB AT2LP	DA1
15		EZ-USB AT2LP
15
	DMINUS		DA0
16	DMINUS	CY7C68320C	DA0
	GND	CY7C68320C	INTRQ
17	GND	CY7C68321C	INTRQ
	VCC		VCC
18	VCC		VCC
	GND	56-pin SSOP	DMACK#

19
	GPIO1		DIOR#
20	GPIO1		DIOR#
	GND		DIOW#
21	GND		DIOW#
	SCL		GND
22	SCL		GND
	SDA		VCC
23	SDA		VCC
	VCC		GND
24	VCC		GND
	DD0		DD7
25	DD0		DD7
	DD1		DD6
26	DD1		DD6
	DD2		DD5
27	DD2		DD5
	DD3		DD4
28	DD3		DD4

Document 001-05809 Rev. *A

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Contents Block Diagram FeaturesCY7C68300C/CY7C68301C CY7C68320C/CY7C68321C EZ-USB AT2LP USB 2.0 to ATA/ATAPI BridgeCY7C68300A Compatibility ApplicationsIntroduction CY4615C EZ-USB AT2LP Reference Design Kit USB Specification versionCY7C68300C EZ-USB AT2LPCY7C68301C 56-pin SSOPENABLE EZ-USB AT2LP CY7C68300C CY7C68301C 56-pin QFNRESET# DD13CY7C68320C EZ-USB AT2LPCY7C68321C 56-pin SSOPARESET# EZ-USB AT2LP CY7C68320C CY7C68321C 56-pin QFNGPIO2 DD15CY7C68321A 100-pin TQFPCY7C68320A USB D-signal See “DPLUS, DMINUS” on page USB D+ signal See “DPLUS, DMINUS” on pagepage PU 10KCY7C68320C/CY7C68321C CY7C68300C/CY7C68301CVBUS detection See “VBUSATAENABLE” on Chip reset See “RESET#” on pageDPLUS, DMINUS “ATAPUEN” on pageSCL, SDA XTALIN, XTALOUTUSB High-Speed SYSIRQATA Interface Pins GPIO PinsDRVPWRVLD LOWPWR#RESET# VBUSATAENABLEATAPUEN PWR500#ATA Command Block ATACB HID Functions for Button ControlsFunctional Overview Byte Table 6. ATACB Field DescriptionsField Name Field Description5-12 Figure 10. Operational Mode Selection Flow Operating ModesOperational Mode Selection Flow Table 7. Command Block Wrapper Bulk-Only Transport Specification . There is a vendor-specificFused Memory Data Normal Mass Storage ModeMfgCB Figure 11. Snapshot of ‘AT2LP Blaster’ Utility EEPROM Organizationwhere the device data length does not match the host data Enable a delay of up to 120 ms at each read of the DRQ bit“Functional Overview” on page 15 for more detail on how length. This allows the CY7C68300C/CY7C68301C to workDetermines if the AT2LP is to do an SRST reset during drive returned on bits 2, 1, and 0 of EP1IN. This bit must be set to CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C does not exist. The USB Mass Storage Class Bulk-Only ConfigurationUSB Bulk In Endpoint Interface DescriptorUSB Bulk Out Endpoint Terminator Page 29 of Number of the channel, must be a zero based value that isDescriptor-Index 0 LANGID CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C unique serial Descriptor-Serial NumberLOADCONFIGDATA READCONFIGDATA Table 12.EEPROM-related Vendor-specific CommandsLabel bmRequestTypeOperating Conditions DC CharacteristicsAbsolute Maximum Ratings Ordering Information AC Electrical CharacteristicsATA Timing Characteristics USB Transceiver CharacteristicsFigure 12. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101 Package DiagramsFigure 13. 56-lead Shrunk Small Outline Package Package Diagrams continuedPage 39 of General PCB Layout Recommendations For USB Mass Storage DesignsFigure 14. 56-Lead QFN 8 x 8 mm LF56A PCB Material Quad Flat Package No Leads QFN Package Design NotesOther Design Considerations Devices With Small Buffers Disclaimers, Trademarks, and CopyrightsIDE Removable Media Devices Issue Date Document History PagedDocument Number ECN NO