Cypress specifications CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C, MfgCB

Page 20
MfgCB

CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

Table 8. Example CfgCB

Offset

CfgCB Byte Descriptions

 

 

 

 

Bits

 

 

 

 

 

7

6

5

4

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

0

bVSCBSignature (set in configuration bytes)

0

0

1

0

 

0

1

0

0

 

 

 

 

 

 

 

 

 

 

 

1

bVSCBSubCommand (must be 0x26)

0

0

1

0

 

0

1

1

0

 

 

 

 

 

 

 

 

 

 

 

2

Reserved (must be set to zero)

0

0

0

0

 

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

3

Data Source (must be set to 0x02)

0

0

0

0

 

0

0

1

0

 

 

 

 

 

 

 

 

 

 

 

4

Start Address (LSB) (must be set to zero)

0

0

0

0

 

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

5

Start Address (MSB) (must be set to zero)

0

0

0

0

 

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

6–15

Reserved (must be set to zero)

0

0

0

0

 

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

MfgCB

The mfg_load and mfg_read vendor-specific commands are passed down through the bulk pipe in the CBWCB portion of the CBW. The format of this MfgCB is shown as follows. Byte0 is a vendor-specific command designator whose value is configurable and set in the AT2LP configuration data. Byte 1 must be 0x27 to identify a MfgCB. Bytes 2 through 15 are reserved and must be set to zero.

The data transfer length is determined by the CBW Data Transfer Length specified in bytes 8 through 11 (dCBWDataTransferLength) of the CBW. The type and direction of the command is determined by the direction bit specified in byte 12, bit 7 (bmCBWFlags) of the CBW.

Table 9. Example MfgCB

Offset

 

MfgCB Byte Description

 

 

 

Bits

 

 

 

 

 

 

7

6

5

4

3

2

1

0

0

0

bVSCBSignature

0

0

1

0

0

1

0

0

 

 

(set in configuration bytes)

 

 

 

 

 

 

 

 

1

1

bVSCBSubCommand

0

0

1

0

0

1

1

1

 

 

(hardcoded 0x27)

 

 

 

 

 

 

 

 

2–15

2–15 Reserved (must be zero)

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

Mfg_load

During a Mfg_load, the AT2LP enters into Manufacturing Test Mode. Manufacturing Test Mode is provided as a means to implement board or system level interconnect tests. During Manufacturing Test Mode operation, all outputs not directly associated with USB operation are controllable. Normal control of the output pins are disabled. Control of the select AT2LP IO pins and their tri-state controls are mapped to the ATAPI data packet associated with this request. (See Table 10 for an explanation of the required Mfg_load data format.) Any data length can be specified, but only bytes 0 through 3 are mapped to pins, so a length of 4 bytes is recommended. To exit Manufacturing Test Mode, a hard reset (toggle RESET#) is required.

Mfg_read

This USB request returns a ’snapshot’ of select AT2LP input pins. AT2LP input pins not directly associated with USB operation can be sampled at any time during Manufacturing Test Mode operation. See Table 10 for an explanation of the Mfg_read data format. Any data length can be specified, but only bytes 0 through 3 contain usable information, so a length of 4 bytes is recommended.

Table 10.Mfg_read and Mfg_load Data Format

Byte

Bits

Read/Load

Function

0

7

R/L

ARESET#

 

6

R

DA2

 

5:4

R/L

CS#[1:0]

 

3

R/L

DRVPWRVLD

 

2:1

R/L

DA[1:0]

 

0

R

INTRQ

 

 

 

 

1

7

L

DD[15:0] High-Z Status

 

 

 

0 = Hi-Z all DD pins

 

 

 

1 = Drive DD pins

 

6

R

MFG_SEL

 

 

 

0 = Mass Storage Mode

 

 

 

1 = Manufacturing Mode

 

5

R

VBUS_ATA_ENABLE

 

4

R

DMARQ

 

3

R

IORDY

 

2

R/L

DMACK#

 

1

R/L

DIOR#

 

0

R/L

DIOW#

 

 

 

 

2

7:0

R/L

DD[7:0]

 

 

 

 

3

7:0

R/L

DD[15:8]

 

 

 

 

Document 001-05809 Rev. *A

Page 20 of 42

[+] Feedback

Image 20
Contents Features Block DiagramCY7C68300C/CY7C68301C CY7C68320C/CY7C68321C EZ-USB AT2LP USB 2.0 to ATA/ATAPI BridgeApplications CY7C68300A CompatibilityIntroduction CY4615C EZ-USB AT2LP Reference Design Kit USB Specification versionEZ-USB AT2LP CY7C68300CCY7C68301C 56-pin SSOPEZ-USB AT2LP CY7C68300C CY7C68301C 56-pin QFN ENABLERESET# DD13EZ-USB AT2LP CY7C68320CCY7C68321C 56-pin SSOPEZ-USB AT2LP CY7C68320C CY7C68321C 56-pin QFN ARESET#GPIO2 DD15CY7C68321A 100-pin TQFPCY7C68320A USB D+ signal See “DPLUS, DMINUS” on page USB D-signal See “DPLUS, DMINUS” on pagepage PU 10KCY7C68300C/CY7C68301C CY7C68320C/CY7C68321CChip reset See “RESET#” on page VBUS detection See “VBUSATAENABLE” on“ATAPUEN” on page DPLUS, DMINUSSCL, SDA XTALIN, XTALOUTSYSIRQ USB High-SpeedGPIO Pins ATA Interface PinsDRVPWRVLD LOWPWR#VBUSATAENABLE RESET#ATAPUEN PWR500#ATA Command Block ATACB HID Functions for Button ControlsFunctional Overview Table 6. ATACB Field Descriptions ByteField Name Field Description5-12 Figure 10. Operational Mode Selection Flow Operating ModesOperational Mode Selection Flow Bulk-Only Transport Specification . There is a vendor-specific Table 7. Command Block WrapperFused Memory Data Normal Mass Storage ModeMfgCB EEPROM Organization Figure 11. Snapshot of ‘AT2LP Blaster’ UtilityEnable a delay of up to 120 ms at each read of the DRQ bit where the device data length does not match the host data“Functional Overview” on page 15 for more detail on how length. This allows the CY7C68300C/CY7C68301C to workDetermines if the AT2LP is to do an SRST reset during drive returned on bits 2, 1, and 0 of EP1IN. This bit must be set to CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Configuration does not exist. The USB Mass Storage Class Bulk-OnlyUSB Bulk In Endpoint Interface DescriptorUSB Bulk Out Endpoint Terminator Number of the channel, must be a zero based value that is Page 29 ofDescriptor-Index 0 LANGID CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Descriptor-Serial Number unique serialLOADCONFIGDATA Table 12.EEPROM-related Vendor-specific Commands READCONFIGDATALabel bmRequestTypeOperating Conditions DC CharacteristicsAbsolute Maximum Ratings AC Electrical Characteristics Ordering InformationATA Timing Characteristics USB Transceiver CharacteristicsPackage Diagrams Figure 12. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101Package Diagrams continued Figure 13. 56-lead Shrunk Small Outline PackagePage 39 of General PCB Layout Recommendations For USB Mass Storage DesignsFigure 14. 56-Lead QFN 8 x 8 mm LF56A PCB Material Quad Flat Package No Leads QFN Package Design NotesOther Design Considerations Devices With Small Buffers Disclaimers, Trademarks, and CopyrightsIDE Removable Media Devices Document History Paged Issue DateDocument Number ECN NO