Cypress specifications CY7C68300C/CY7C68301C, CY7C68320C/CY7C68321C, 5-12

Page 17
5–12

 

 

 

 

CY7C68300C/CY7C68301C

 

 

 

 

 

CY7C68320C/CY7C68321C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 6. ATACB Field Descriptions (continued)

 

 

 

 

 

 

 

 

Byte

Field Name

Field Description

 

 

 

 

 

 

 

3

bmATACBRegisterSelect

This field controls which of the taskfile register read or write accesses occur.

 

 

 

 

 

Taskfile read data is always 8 bytes in length, and unselected register data are

 

 

 

 

 

returned as 0x00. Register accesses occur in sequential order as outlined

 

 

 

 

 

below (0 to 7):

 

 

 

 

 

Bit 0 (0x3F6) Device Control/Alternate Status

 

 

 

 

 

Bit 1 (0x1F1) Features/Error

 

 

 

 

 

Bit 2 (0x1F2) Sector Count

 

 

 

 

 

Bit 3 (0x1F3) Sector Number

 

 

 

 

 

Bit 4 (0x1F4) Cylinder Low

 

 

 

 

 

Bit 5 (0x1F5) Cylinder High

 

 

 

 

 

Bit 6 (0x1F6) Device/Head

 

 

 

 

 

Bit 7 (0x1F7) Command/Status

 

 

 

 

 

 

 

4

bATACBTransferBlockCount

This value indicates the maximum requested block size be in 512-byte incre-

 

 

 

 

 

ments. This value must be set to the last value used for the ’Sectors per block’

 

 

 

 

 

in the SET_MULTIPLE_MODE command. Legal values are 0, 1, 2, 4, 8, 16,

 

 

 

 

 

32, 64, and 128 where 0 indicates 256 sectors per block. A command failed

 

 

 

 

 

status is returned if an illegal value is used in the ATACB.

 

 

5–12

bATACBTaskFileWriteData

These bytes contain ATA register data used with ATA command or PIO write

 

 

 

 

 

operations. Only registers selected in bmATACBRegisterSelect are required to

 

 

 

 

 

hold valid data when accessed. The registers are as follows.

 

 

 

 

 

ATACB Address Offset 0x05 (0x3F6) – Device Control

 

 

 

 

 

ATACB Address Offset 0x06 (0x1F1) – Features

 

 

 

 

 

ATACB Address Offset 0x07 (0x1F2) – Sector Count

 

 

 

 

 

ATACB Address Offset 0x08 (0x1F3) – Sector Number

 

 

 

 

 

ATACB Address Offset 0x09 (0x1F4) – Cylinder Low

 

 

 

 

 

ATACB Address Offset 0x0A (0x1F5) – Cylinder High

 

 

 

 

 

ATACB Address Offset 0x0B (0x1F6) – Device

 

 

 

 

 

ATACB Address Offset 0x0C (0x1F7) – Command

 

 

 

 

 

 

 

13–15

Reserved

These bytes must be set to 0x00 for ATACB commands.

 

 

 

 

 

 

 

Document 001-05809 Rev. *A

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Contents Block Diagram FeaturesCY7C68300C/CY7C68301C CY7C68320C/CY7C68321C EZ-USB AT2LP USB 2.0 to ATA/ATAPI BridgeCY7C68300A Compatibility ApplicationsIntroduction CY4615C EZ-USB AT2LP Reference Design Kit USB Specification versionCY7C68300C EZ-USB AT2LPCY7C68301C 56-pin SSOPENABLE EZ-USB AT2LP CY7C68300C CY7C68301C 56-pin QFNRESET# DD13CY7C68320C EZ-USB AT2LPCY7C68321C 56-pin SSOPARESET# EZ-USB AT2LP CY7C68320C CY7C68321C 56-pin QFNGPIO2 DD15CY7C68321A 100-pin TQFPCY7C68320A USB D-signal See “DPLUS, DMINUS” on page USB D+ signal See “DPLUS, DMINUS” on pagepage PU 10KCY7C68320C/CY7C68321C CY7C68300C/CY7C68301CVBUS detection See “VBUSATAENABLE” on Chip reset See “RESET#” on pageDPLUS, DMINUS “ATAPUEN” on pageSCL, SDA XTALIN, XTALOUTUSB High-Speed SYSIRQATA Interface Pins GPIO PinsDRVPWRVLD LOWPWR#RESET# VBUSATAENABLEATAPUEN PWR500#ATA Command Block ATACB HID Functions for Button ControlsFunctional Overview Byte Table 6. ATACB Field DescriptionsField Name Field Description5-12 Figure 10. Operational Mode Selection Flow Operating ModesOperational Mode Selection Flow Table 7. Command Block Wrapper Bulk-Only Transport Specification . There is a vendor-specificFused Memory Data Normal Mass Storage ModeMfgCB Figure 11. Snapshot of ‘AT2LP Blaster’ Utility EEPROM Organizationwhere the device data length does not match the host data Enable a delay of up to 120 ms at each read of the DRQ bit“Functional Overview” on page 15 for more detail on how length. This allows the CY7C68300C/CY7C68301C to workDetermines if the AT2LP is to do an SRST reset during drive returned on bits 2, 1, and 0 of EP1IN. This bit must be set to CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C does not exist. The USB Mass Storage Class Bulk-Only ConfigurationUSB Bulk In Endpoint Interface DescriptorUSB Bulk Out Endpoint Terminator Page 29 of Number of the channel, must be a zero based value that isDescriptor-Index 0 LANGID CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C unique serial Descriptor-Serial NumberLOADCONFIGDATA READCONFIGDATA Table 12.EEPROM-related Vendor-specific CommandsLabel bmRequestTypeOperating Conditions DC CharacteristicsAbsolute Maximum Ratings Ordering Information AC Electrical CharacteristicsATA Timing Characteristics USB Transceiver CharacteristicsFigure 12. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101 Package DiagramsFigure 13. 56-lead Shrunk Small Outline Package Package Diagrams continuedPage 39 of General PCB Layout Recommendations For USB Mass Storage DesignsFigure 14. 56-Lead QFN 8 x 8 mm LF56A PCB Material Quad Flat Package No Leads QFN Package Design NotesOther Design Considerations Devices With Small Buffers Disclaimers, Trademarks, and CopyrightsIDE Removable Media Devices Issue Date Document History PagedDocument Number ECN NO