Cypress specifications CY7C68300C/CY7C68301C, CY7C68320C/CY7C68321C, page

Page 9
CY7C68300C/CY7C68301C

 

 

 

 

 

 

 

 

 

CY7C68300C/CY7C68301C

 

 

 

 

 

 

 

 

 

CY7C68320C/CY7C68321C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 1. AT2LP Pin Descriptions

 

 

 

 

 

 

Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode) (continued)

 

 

 

 

 

 

 

 

 

 

 

100

56

56

 

 

Pin Name

Pin

Default State

Pin Description

 

TQFP

QFN

SSOP

 

 

Type

at Startup

 

 

 

 

 

 

 

30

16

23

 

 

SDA

IO

 

Data signal for I2C interface. (See “SCL, SDA” on

 

 

 

 

 

 

 

 

 

page 11).

 

 

 

 

 

 

 

 

 

Apply a 2.2k pull up resistor.

 

31

N/A

N/A

 

 

NC

 

 

No connect.

 

32

 

 

 

 

 

 

 

 

 

 

33

17

24

 

 

VCC

PWR

 

VCC. Connect to 3.3V power source.

 

34

18

25

 

 

DD0

IO[1]

Hi-Z

ATA data bit 0.

 

35

19

26

 

 

DD1

IO[1]

Hi-Z

ATA data bit 1.

 

36

20

27

 

 

DD2

IO[1]

Hi-Z

ATA data bit 2.

 

37

21

28

 

 

DD3

IO[1]

Hi-Z

ATA data bit 3.

 

38

N/A

N/A

 

 

VCC

PWR

 

VCC. Connect to 3.3V power source.

 

39

N/A

N/A

 

 

GND

GND

 

Ground.

 

40

N/A

N/A

 

 

NC

NC

 

No connect.

 

 

 

 

 

 

 

 

 

 

 

41

N/A

N/A

 

 

GND

 

 

Ground.

 

 

 

 

 

 

 

 

 

 

 

42

N/A

N/A

 

 

NC

NC

 

No connect.

 

43

N/A

N/A

 

 

GND

 

 

Ground.

 

 

 

 

 

 

 

 

 

 

 

44

22

29

 

 

DD4

IO[1]

Hi-Z

ATA data bit 4.

 

45

23

30

 

 

DD5

IO[1]

Hi-Z

ATA data bit 5.

 

46

24

31

 

 

DD6

IO[1]

Hi-Z

ATA data bit 6.

 

47

25

32

 

 

DD7

IO[1]

Hi-Z

ATA data bit 7. Apply a 1k pull down to GND.

 

48

26

33

 

 

GND

GND

 

Ground.

 

49

27

34

 

 

VCC

PWR

 

VCC. Connect to 3.3V power source.

 

50

28

35

 

 

GND

GND

 

Ground.

 

 

 

 

 

 

 

 

 

 

 

51

N/A

N/A

 

 

NC

NC

 

No connect.

 

52

 

 

 

 

 

 

 

 

 

 

53

N/A

N/A

 

 

VCC

PWR

 

VCC. Connect to 3.3V power source.

 

54

29

36

 

 

DIOW#[2]

O/Z[1]

Driven HIGH

ATA control.

 

 

 

 

 

 

 

 

(CMOS)

 

 

 

55

30

37

 

 

DIOR#

O/Z[1]

Driven HIGH

ATA control.

 

 

 

 

 

 

 

 

(CMOS)

 

 

 

56

31

38

 

 

DMACK#

O/Z[1]

Driven HIGH

ATA control.

 

 

 

 

 

 

 

 

(CMOS)

 

 

 

57

N/A

N/A

 

 

NC

NC

 

No connect.

 

 

 

 

 

 

 

 

 

 

58

N/A

N/A

 

LOWPWR#

O

 

USB suspend indicator. (See “LOWPWR#” on

 

 

 

 

 

 

 

 

 

page 13).

 

59

N/A

N/A

 

 

NC

NC

 

No connect.

 

60

 

 

 

 

 

 

 

 

 

 

61

 

 

 

 

 

 

 

 

 

 

62

N/A

N/A

 

VBUSPWRD

I

Input

Bus-powered mode selector. (See “VBUSPWRD” on

 

 

 

 

 

 

 

 

 

page 14).

 

63

N/A

N/A

 

 

NC

NC

 

No connect.

 

64

 

 

 

 

 

 

 

 

 

 

65

N/A

N/A

 

 

GND

GND

 

Ground.

 

 

 

 

 

 

 

 

 

 

 

66

32

39

 

 

VCC

PWR

 

VCC. Connect to 3.3V power source.

 

67

33

40

 

 

INTRQ

I[1]

Input

ATA interrupt request.

Document 001-05809 Rev. *A

 

 

 

 

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Contents Block Diagram FeaturesCY7C68300C/CY7C68301C CY7C68320C/CY7C68321C EZ-USB AT2LP USB 2.0 to ATA/ATAPI BridgeCY7C68300A Compatibility ApplicationsIntroduction CY4615C EZ-USB AT2LP Reference Design Kit USB Specification versionCY7C68300C EZ-USB AT2LPCY7C68301C 56-pin SSOPENABLE EZ-USB AT2LP CY7C68300C CY7C68301C 56-pin QFNRESET# DD13CY7C68320C EZ-USB AT2LPCY7C68321C 56-pin SSOPARESET# EZ-USB AT2LP CY7C68320C CY7C68321C 56-pin QFNGPIO2 DD15100-pin TQFP CY7C68320ACY7C68321A USB D-signal See “DPLUS, DMINUS” on page USB D+ signal See “DPLUS, DMINUS” on pagepage PU 10KCY7C68320C/CY7C68321C CY7C68300C/CY7C68301CVBUS detection See “VBUSATAENABLE” on Chip reset See “RESET#” on pageDPLUS, DMINUS “ATAPUEN” on pageSCL, SDA XTALIN, XTALOUTUSB High-Speed SYSIRQATA Interface Pins GPIO PinsDRVPWRVLD LOWPWR#RESET# VBUSATAENABLEATAPUEN PWR500#HID Functions for Button Controls Functional OverviewATA Command Block ATACB Byte Table 6. ATACB Field DescriptionsField Name Field Description5-12 Operating Modes Operational Mode Selection FlowFigure 10. Operational Mode Selection Flow Table 7. Command Block Wrapper Bulk-Only Transport Specification . There is a vendor-specificFused Memory Data Normal Mass Storage ModeMfgCB Figure 11. Snapshot of ‘AT2LP Blaster’ Utility EEPROM Organizationwhere the device data length does not match the host data Enable a delay of up to 120 ms at each read of the DRQ bit“Functional Overview” on page 15 for more detail on how length. This allows the CY7C68300C/CY7C68301C to workDetermines if the AT2LP is to do an SRST reset during drive returned on bits 2, 1, and 0 of EP1IN. This bit must be set to CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C does not exist. The USB Mass Storage Class Bulk-Only ConfigurationInterface Descriptor USB Bulk Out EndpointUSB Bulk In Endpoint Terminator Page 29 of Number of the channel, must be a zero based value that isDescriptor-Index 0 LANGID CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C unique serial Descriptor-Serial NumberLOADCONFIGDATA READCONFIGDATA Table 12.EEPROM-related Vendor-specific CommandsLabel bmRequestTypeDC Characteristics Absolute Maximum RatingsOperating Conditions Ordering Information AC Electrical CharacteristicsATA Timing Characteristics USB Transceiver CharacteristicsFigure 12. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A101 Package DiagramsFigure 13. 56-lead Shrunk Small Outline Package Package Diagrams continuedGeneral PCB Layout Recommendations For USB Mass Storage Designs Figure 14. 56-Lead QFN 8 x 8 mm LF56APage 39 of Quad Flat Package No Leads QFN Package Design Notes Other Design ConsiderationsPCB Material Disclaimers, Trademarks, and Copyrights IDE Removable Media DevicesDevices With Small Buffers Issue Date Document History PagedDocument Number ECN NO