Cypress CY8C24123A manual Register Map Bank 1 Table Configuration Space

Page 16

CY8C24123A

CY8C24223A, CY8C24423A

Table 9. Register Map Bank 0 Table: User Space (continued)

Name

Addr

Access

Name

Addr

Access

Name

Addr

Access

Name

Addr

Access

(0,Hex)

(0,Hex)

(0,Hex)

(0,Hex)

 

3E

 

 

7E

 

 

BE

 

CPU_SCR1

FE

#

 

3F

 

 

7F

 

 

BF

 

CPU_SCR0

FF

#

Blank fields are

Reserved and must not be accessed.

 

 

# Access is bit specific.

 

 

 

 

Table 10. Register Map Bank 1 Table: Configuration Space

Name

Addr

Access

Name

Addr

Access

Name

Addr

Access

Name

Addr

Access

(1,Hex)

(1,Hex)

(1,Hex)

(1,Hex)

PRT0DM0

00

RW

 

40

 

ASC10CR0

80

RW

 

C0

 

PRT0DM1

01

RW

 

41

 

ASC10CR1

81

RW

 

C1

 

PRT0IC0

02

RW

 

42

 

ASC10CR2

82

RW

 

C2

 

PRT0IC1

03

RW

 

43

 

ASC10CR3

83

RW

 

C3

 

PRT1DM0

04

RW

 

44

 

ASD11CR0

84

RW

 

C4

 

PRT1DM1

05

RW

 

45

 

ASD11CR1

85

RW

 

C5

 

PRT1IC0

06

RW

 

46

 

ASD11CR2

86

RW

 

C6

 

PRT1IC1

07

RW

 

47

 

ASD11CR3

87

RW

 

C7

 

PRT2DM0

08

RW

 

48

 

 

88

 

 

C8

 

PRT2DM1

09

RW

 

49

 

 

89

 

 

C9

 

PRT2IC0

0A

RW

 

4A

 

 

8A

 

 

CA

 

PRT2IC1

0B

RW

 

4B

 

 

8B

 

 

CB

 

 

0C

 

 

4C

 

 

8C

 

 

CC

 

 

0D

 

 

4D

 

 

8D

 

 

CD

 

 

0E

 

 

4E

 

 

8E

 

 

CE

 

 

0F

 

 

4F

 

 

8F

 

 

CF

 

 

10

 

 

50

 

ASD20CR0

90

RW

GDI_O_IN

D0

RW

 

11

 

 

51

 

ASD20CR1

91

RW

GDI_E_IN

D1

RW

 

12

 

 

52

 

ASD20CR2

92

RW

GDI_O_OU

D2

RW

 

13

 

 

53

 

ASD20CR3

93

RW

GDI_E_OU

D3

RW

 

14

 

 

54

 

ASC21CR0

94

RW

 

D4

 

 

15

 

 

55

 

ASC21CR1

95

RW

 

D5

 

 

16

 

 

56

 

ASC21CR2

96

RW

 

D6

 

 

17

 

 

57

 

ASC21CR3

97

RW

 

D7

 

 

18

 

 

58

 

 

98

 

 

D8

 

 

19

 

 

59

 

 

99

 

 

D9

 

 

1A

 

 

5A

 

 

9A

 

 

DA

 

 

1B

 

 

5B

 

 

9B

 

 

DB

 

 

1C

 

 

5C

 

 

9C

 

 

DC

 

 

1D

 

 

5D

 

 

9D

 

OSC_GO_EN

DD

RW

 

1E

 

 

5E

 

 

9E

 

OSC_CR4

DE

RW

 

1F

 

 

5F

 

 

9F

 

OSC_CR3

DF

RW

DBB00FN

20

RW

CLK_CR0

60

RW

 

A0

 

OSC_CR0

E0

RW

DBB00IN

21

RW

CLK_CR1

61

RW

 

A1

 

OSC_CR1

E1

RW

DBB00OU

22

RW

ABF_CR0

62

RW

 

A2

 

OSC_CR2

E2

RW

 

23

 

AMD_CR0

63

RW

 

A3

 

VLT_CR

E3

RW

DBB01FN

24

RW

 

64

 

 

A4

 

VLT_CMP

E4

R

DBB01IN

25

RW

 

65

 

 

A5

 

 

E5

 

DBB01OU

26

RW

AMD_CR1

66

RW

 

A6

 

 

E6

 

 

27

 

ALT_CR0

67

RW

 

A7

 

 

E7

 

DCB02FN

28

RW

 

68

 

 

A8

 

IMO_TR

E8

W

DCB02IN

29

RW

 

69

 

 

A9

 

ILO_TR

E9

W

DCB02OU

2A

RW

 

6A

 

 

AA

 

BDG_TR

EA

RW

 

2B

 

 

6B

 

 

AB

 

ECO_TR

EB

W

DCB03FN

2C

RW

 

6C

 

 

AC

 

 

EC

 

DCB03IN

2D

RW

 

6D

 

 

AD

 

 

ED

 

DCB03OU

2E

RW

 

6E

 

 

AE

 

 

EE

 

 

2F

 

 

6F

 

 

AF

 

 

EF

 

 

30

 

ACB00CR3

70

RW

RDI0RI

B0

RW

 

F0

 

 

31

 

ACB00CR0

71

RW

RDI0SYN

B1

RW

 

F1

 

 

32

 

ACB00CR1

72

RW

RDI0IS

B2

RW

 

F2

 

 

33

 

ACB00CR2

73

RW

RDI0LT0

B3

RW

 

F3

 

 

34

 

ACB01CR3

74

RW

RDI0LT1

B4

RW

 

F4

 

 

35

 

ACB01CR0

75

RW

RDI0RO0

B5

RW

 

F5

 

 

36

 

ACB01CR1

76

RW

RDI0RO1

B6

RW

 

F6

 

Blank fields are

Reserved and must not be accessed.

 

 

# Access is bit specific.

 

 

 

 

Document Number: 38-12028 Rev. *I

 

 

 

 

 

 

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Contents Logic Block Diagram FeaturesCypress Semiconductor Corporation 198 Champion Court PSoC Core PSoC Functional OverviewDigital System Analog System Block Diagram Analog SystemPSoC Device Characteristics PSoC Part Getting StartedAdditional System Resources Consultants Technical Support Application NotesDevelopment Tools PSoC Designer Software SubsystemsDevice Editor Design BrowserDesigning with User Modules Hardware ToolsDevice Editor Application EditorDocument Conventions Acronyms UsedUnits of Measure Numeric NamingPinouts Pin Part Pinoutt2PDIP 3SOICPin Part Pinout Pin Definitions 20-Pin PDIP, SSOP, and SoicSCL, ISSP-SCLK SDA, ISSP-SDATAActive High External Reset with Internal CY8C24423A 28-Pin PSoC DeviceSwitch Mode Pump SMP Connection Pin Definitions 32-Pin QFNTo External Components required ExtclkOCD Not for Production OCD Hclk OCD CclkRegister Reference Register ConventionsRegister Mapping Tables Abbreviations UsedName Addr Access Hex Register Map Bank 0 Table User SpaceRegister Map Bank 1 Table Configuration Space ACB01CR2 Cpuf CPUSCR1 CPUSCR0 Electrical Specifications Units of Measure Symbol Unit of MeasureOperating Temperature Absolute Maximum Ratings Symbol Description Min Typ UnitsOperating Temperature Symbol Description Min Typ Max Units Absolute Maximum RatingsDC Electrical Characteristics DC Chip-Level SpecificationsDC General Purpose IO Specifications DC Operational Amplifier Specifications Psrr OAAverage Input Offset Voltage Drift DC Low Power Comparator Specifications Low power comparator LPC reference Vdd Voltage rangeLPC supply current LPC voltage offset Document Number 38-12028 Rev. *IDC Analog Output Buffer Specifications Psrr OBDC Switch Mode Pump Specifications Switching Duty Cycle Switching Frequency MHzOutput Voltage Ripple depends on DC Analog Reference Specifications Bandgap Voltage Reference Agnd = Vdd/2Agnd = 2 x BandGap BG + Agnd = P24 P24 = Vdd/2 Agnd = 2 x BandGap Not Allowed Agnd = P24 P24 = Vdd/2CY8C24123A CY8C24223A, CY8C24423A DC Analog PSoC Block Specifications DC POR, SMP, and LVD SpecificationsDC Programming Specifications AC Chip-Level Specifications AC Electrical CharacteristicsDC24M MHz Refer to the AC Digital Block Nominal Specifications CPU Frequency 2.7V NominalDC12M MHz Duty Cycle Jitter12M1P MHz Period Jitter IMOGain Enable32K Select AC General Purpose IO Specifications AC Operational Amplifier Specifications Noise at 1 kHz Power = Medium, Opamp Bias = HighBW OA NV/rt-HzCY8C24123A CY8C24223A, CY8C24423A Typical Agnd Noise with P24 Bypass AC Low Power Comparator Specifications AC Digital Block SpecificationsCrcprs SpimPRS CRCLarge Signal Bandwidth, 1V pp, 3dB BW, 100 pF Load AC Analog Output Buffer SpecificationsBW OB AC External Clock Specifications AC Programming Specifications AC I2C SpecificationsBus Free Time Between a Stop and Start Condition Setup Time for Stop ConditionPulse Width of spikes are suppressed by Input filter Packaging Dimensions Packaging InformationPin 150-Mil Soic Pin 210-Mil Ssop 51-85014 *D Pin 5x5 mm QFN Pin Sawn QFN Package Capacitance on Crystal Pins Solder Reflow Peak TemperatureTypical Package Capacitance on Crystal Pins Thermal ImpedancesDevelopment Tool Selection SoftwareDevelopment Kits Evaluation ToolsAccessories Emulation and Programming Emulation and Programming AccessoriesDevice Programmers Third Party Tools Build a PSoC Emulator into Your BoardOrdering Code Definitions Ordering InformationSawn QFN Document History Orig. Submission Description of Change DateWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB