Cypress CY8C24123A DC Analog Reference Specifications, Bandgap Voltage Reference Agnd = Vdd/2

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CY8C24123A

CY8C24223A, CY8C24423A

DC Analog Reference Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high.

Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the AGND.

Table 25. 5V DC Analog Reference Specifications

Symbol

Description

 

Min

Typ

Max

Units

BG

Bandgap Voltage Reference

 

1.28

1.30

1.33

V

–

AGND = Vdd/2

 

Vdd/2 - 0.04

Vdd/2 - 0.01

Vdd/2 + 0.007

V

–

AGND = 2 x BandGap

 

2 x BG - 0.048

2 x BG - 0.030

2 x BG + 0.024

V

–

AGND = P2[4] (P2[4] = Vdd/2)

 

P2[4] - 0.011

P2[4]

P2[4] + 0.011

V

–

AGND = BandGap

 

BG - 0.009

BG + 0.008

BG + 0.016

V

–

AGND = 1.6 x BandGap

 

1.6 x BG - 0.022

1.6 x BG - 0.010

1.6 x BG + 0.018

V

–

AGND Block to Block Variation

 

-0.034

0.000

0.034

V

 

(AGND = Vdd/2)

 

 

 

 

 

–

RefHi = Vdd/2 + BandGap

 

Vdd/2 + BG - 0.10

Vdd/2 + BG

Vdd/2 + BG + 0.10

V

–

RefHi = 3 x BandGap

 

3 x BG - 0.06

3 x BG

3 x BG + 0.06

V

–

RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)

 

2 x BG + P2[6] - 0.113

2 x BG + P2[6] - 0.018

2 x BG + P2[6] + 0.077

V

–

RefHi = P2[4] + BandGap (P2[4] = Vdd/2)

 

P2[4] + BG - 0.130

P2[4] + BG - 0.016

P2[4] + BG + 0.098

V

–

RefHi = P2[4] + P2[6] (P2[4] = Vdd/2

 

P2[4] + P2[6] - 0.133

P2[4] + P2[6] - 0.016

P2[4] + P2[6]+ 0.100

V

 

P2[6] = 1.3V)

 

 

 

 

 

–

RefHi = 3.2 x BandGap

 

3.2 x BG - 0.112

3.2 x BG

3.2 x BG + 0.076

V

–

RefLo = Vdd/2 – BandGap

 

Vdd/2 - BG - 0.04

Vdd/2 - BG + 0.024

Vdd/2 - BG + 0.04

V

–

RefLo = BandGap

 

BG - 0.06

BG

BG + 0.06

V

–

RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)

 

2 x BG - P2[6] - 0.084

2 x BG - P2[6] + 0.025

2 x BG - P2[6] + 0.134

V

–

RefLo = P2[4] – BandGap (P2[4] = Vdd/2)

 

P2[4] - BG - 0.056

P2[4] - BG + 0.026

P2[4] - BG + 0.107

V

–

RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,

 

P2[4] - P2[6] - 0.057

P2[4] - P2[6] + 0.026

P2[4] - P2[6] + 0.110

V

 

P2[6] = 1.3V)

 

 

 

 

 

Table 26. 3.3V DC Analog Reference Specifications

 

 

 

 

 

 

 

 

 

 

Symbol

Description

 

Min

Typ

Max

Units

BG

Bandgap Voltage Reference

 

1.28

1.30

1.33

V

–

AGND = Vdd/2

 

Vdd/2 - 0.03

Vdd/2 - 0.01

Vdd/2 + 0.005

V

–

AGND = 2 x BandGap

 

 

Not Allowed

 

 

–

AGND = P2[4] (P2[4] = Vdd/2)

 

P2[4] - 0.008

P2[4] + 0.001

P2[4] + 0.009

V

–

AGND = BandGap

 

BG - 0.009

BG + 0.005

BG + 0.015

V

–

AGND = 1.6 x BandGap

 

1.6 x BG - 0.027

1.6 x BG - 0.010

1.6 x BG + 0.018

V

–

AGND Column to Column Variation

 

-0.034

0.000

0.034

mV

 

(AGND = Vdd/2)

 

 

 

 

 

–

RefHi = Vdd/2 + BandGap

 

 

Not Allowed

 

 

–

RefHi = 3 x BandGap

 

 

Not Allowed

 

 

–

RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)

 

 

Not Allowed

 

 

–

RefHi = P2[4] + BandGap (P2[4] = Vdd/2)

 

 

Not Allowed

 

 

Document Number: 38-12028 Rev. *I

 

 

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Contents Logic Block Diagram FeaturesCypress Semiconductor Corporation 198 Champion Court PSoC Core PSoC Functional OverviewDigital System Analog System Block Diagram Analog SystemPSoC Device Characteristics PSoC Part Getting StartedAdditional System Resources Consultants Technical Support Application NotesDevelopment Tools PSoC Designer Software SubsystemsDevice Editor Design BrowserDesigning with User Modules Hardware ToolsDevice Editor Application EditorDocument Conventions Acronyms UsedUnits of Measure Numeric NamingPinouts Pin Part Pinoutt2PDIP 3SOICPin Part Pinout Pin Definitions 20-Pin PDIP, SSOP, and SoicSCL, ISSP-SCLK SDA, ISSP-SDATAActive High External Reset with Internal CY8C24423A 28-Pin PSoC DeviceSwitch Mode Pump SMP Connection Pin Definitions 32-Pin QFNTo External Components required ExtclkOCD Not for ProductionOCD Hclk OCD CclkRegister Reference Register ConventionsRegister Mapping Tables Abbreviations UsedName Addr Access Hex Register Map Bank 0 Table User SpaceRegister Map Bank 1 Table Configuration Space ACB01CR2 Cpuf CPUSCR1 CPUSCR0 Electrical Specifications Units of Measure Symbol Unit of MeasureOperating Temperature Absolute Maximum Ratings Symbol Description Min Typ UnitsOperating Temperature Symbol Description Min Typ Max Units Absolute Maximum RatingsDC Electrical Characteristics DC Chip-Level SpecificationsDC General Purpose IO Specifications DC Operational Amplifier Specifications Psrr OAAverage Input Offset Voltage Drift DC Low Power Comparator Specifications Low power comparator LPC reference Vdd Voltage rangeLPC supply current LPC voltage offset Document Number 38-12028 Rev. *IDC Analog Output Buffer Specifications Psrr OBDC Switch Mode Pump Specifications Switching Duty Cycle Switching Frequency MHzOutput Voltage Ripple depends on DC Analog Reference Specifications Bandgap Voltage Reference Agnd = Vdd/2Agnd = 2 x BandGap BG + Agnd = P24 P24 = Vdd/2 Agnd = 2 x BandGap Not Allowed Agnd = P24 P24 = Vdd/2CY8C24123A CY8C24223A, CY8C24423A DC Analog PSoC Block Specifications DC POR, SMP, and LVD SpecificationsDC Programming Specifications AC Chip-Level Specifications AC Electrical CharacteristicsDC24M MHz Refer to the AC Digital Block Nominal Specifications CPU Frequency 2.7V NominalDC12M MHz Duty Cycle Jitter12M1P MHz Period Jitter IMOGain Enable32K Select AC General Purpose IO Specifications AC Operational Amplifier Specifications Noise at 1 kHz Power = Medium, Opamp Bias = HighBW OA NV/rt-HzCY8C24123A CY8C24223A, CY8C24423A Typical Agnd Noise with P24 Bypass AC Low Power Comparator Specifications AC Digital Block SpecificationsCrcprs SpimPRS CRCLarge Signal Bandwidth, 1V pp, 3dB BW, 100 pF Load AC Analog Output Buffer SpecificationsBW OB AC External Clock Specifications AC Programming Specifications AC I2C SpecificationsBus Free Time Between a Stop and Start Condition Setup Time for Stop ConditionPulse Width of spikes are suppressed by Input filter Packaging Dimensions Packaging InformationPin 150-Mil Soic Pin 210-Mil Ssop 51-85014 *D Pin 5x5 mm QFN Pin Sawn QFN Package Capacitance on Crystal Pins Solder Reflow Peak TemperatureTypical Package Capacitance on Crystal Pins Thermal ImpedancesDevelopment Tool Selection SoftwareDevelopment Kits Evaluation ToolsAccessories Emulation and Programming Emulation and Programming AccessoriesDevice Programmers Third Party Tools Build a PSoC Emulator into Your BoardOrdering Code Definitions Ordering InformationSawn QFN Document History Orig. Submission Description of Change DateWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB

CY8C24123A specifications

The Cypress CY8C24123A is a prominent member of the PSoC (Programmable System-on-Chip) family, which integrates a microcontroller with programmable analog and digital components on a single chip. Designed for low-power applications, the CY8C24123A offers a compelling mix of features and technologies that make it a popular choice for embedded system developers.

One of the standout features of the CY8C24123A is its low power consumption, which allows it to extend battery life in portable applications. It operates at a voltage range of 1.71V to 5.5V, making it versatile for various power supply options. This device is equipped with a 24 MHz CPU that efficiently executes tasks while keeping energy usage minimal.

The chip boasts a rich set of programmable peripherals, including analog components such as operational amplifiers, comparators, and DACs, enabling designers to create custom signal processing pathways. These features are complemented by a variety of digital peripherals, like timers, UART, I2C, and SPI interfaces, which facilitate communication with other devices and microcontrollers. The integration of these components reduces the need for external components, leading to a more compact design and lower overall system costs.

Moreover, the CY8C24123A includes Flash memory (up to 2 KB) and SRAM (256 bytes), providing ample storage for application code and data. This Flash memory is reprogrammable, enabling developers to update their applications easily without needing to replace the chip.

Another defining characteristic of the CY8C24123A is its programmability. The device can be configured and programmed using the Cypress PSoC Designer software, which allows developers to design and simulate their applications in a user-friendly environment. The combination of hardware-based flexibility and software configuration provides a robust platform for creating custom solutions tailored to specific application requirements.

Overall, the Cypress CY8C24123A stands out for its balance of performance, programmability, and power efficiency. Its integration of programmable analog and digital blocks makes it suitable for a wide range of applications, including industrial control, consumer electronics, and automotive systems. The ability to customize the chip's functionality further boosts its appeal, making it an excellent choice for developers seeking a versatile and efficient solution for their embedded projects.
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