Contents
Logic Block Diagram
Features
Cypress Semiconductor Corporation 198 Champion Court
PSoC Core
PSoC Functional Overview
Digital System
Analog System
Analog System Block Diagram
Getting Started
PSoC Device Characteristics PSoC Part
Additional System Resources
Consultants Technical Support Application Notes
PSoC Designer Software Subsystems
Development Tools
Device Editor
Design Browser
Hardware Tools
Designing with User Modules
Device Editor
Application Editor
Acronyms Used
Document Conventions
Units of Measure
Numeric Naming
Pin Part Pinoutt
Pinouts
2PDIP
3SOIC
Pin Definitions 20-Pin PDIP, SSOP, and Soic
Pin Part Pinout
SCL, ISSP-SCLK
SDA, ISSP-SDATA
CY8C24423A 28-Pin PSoC Device
Active High External Reset with Internal
Pin Definitions 32-Pin QFN
Switch Mode Pump SMP Connection
To External Components required
Extclk
Not for Production
OCD
OCD Cclk
OCD Hclk
Register Conventions
Register Reference
Register Mapping Tables
Abbreviations Used
Register Map Bank 0 Table User Space
Name Addr Access Hex
Register Map Bank 1 Table Configuration Space
ACB01CR2 Cpuf CPUSCR1 CPUSCR0
Units of Measure Symbol Unit of Measure
Electrical Specifications
Absolute Maximum Ratings Symbol Description Min Typ Units
Operating Temperature
Operating Temperature Symbol Description Min Typ Max Units
Absolute Maximum Ratings
DC Chip-Level Specifications
DC Electrical Characteristics
DC General Purpose IO Specifications
Psrr OA
DC Operational Amplifier Specifications
Average Input Offset Voltage Drift
Low power comparator LPC reference Vdd Voltage range
DC Low Power Comparator Specifications
LPC supply current
LPC voltage offset Document Number 38-12028 Rev. *I
Psrr OB
DC Analog Output Buffer Specifications
DC Switch Mode Pump Specifications
Switching Duty Cycle
Switching Frequency MHz
Output Voltage Ripple depends on
Bandgap Voltage Reference Agnd = Vdd/2
DC Analog Reference Specifications
Agnd = 2 x BandGap BG + Agnd = P24 P24 = Vdd/2
Agnd = 2 x BandGap Not Allowed Agnd = P24 P24 = Vdd/2
CY8C24123A CY8C24223A, CY8C24423A
DC POR, SMP, and LVD Specifications
DC Analog PSoC Block Specifications
DC Programming Specifications
AC Chip-Level Specifications
AC Electrical Characteristics
DC24M
CPU Frequency 2.7V Nominal
MHz Refer to the AC Digital Block Nominal Specifications
DC12M
MHz Duty Cycle Jitter12M1P MHz Period Jitter IMO
Gain
Enable
32K Select
AC General Purpose IO Specifications
Noise at 1 kHz Power = Medium, Opamp Bias = High
AC Operational Amplifier Specifications
BW OA
NV/rt-Hz
CY8C24123A CY8C24223A, CY8C24423A
Typical Agnd Noise with P24 Bypass
AC Digital Block Specifications
AC Low Power Comparator Specifications
Crcprs
Spim
CRC
PRS
Large Signal Bandwidth, 1V pp, 3dB BW, 100 pF Load
AC Analog Output Buffer Specifications
BW OB
AC External Clock Specifications
AC I2C Specifications
AC Programming Specifications
Bus Free Time Between a Stop and Start Condition
Setup Time for Stop Condition
Pulse Width of spikes are suppressed by Input filter
Packaging Information
Packaging Dimensions
Pin 150-Mil Soic
Pin 210-Mil Ssop
51-85014 *D
Pin 5x5 mm QFN
Pin Sawn QFN Package
Solder Reflow Peak Temperature
Capacitance on Crystal Pins
Typical Package Capacitance on Crystal Pins
Thermal Impedances
Software
Development Tool Selection
Development Kits
Evaluation Tools
Emulation and Programming Accessories
Accessories Emulation and Programming
Device Programmers
Third Party Tools Build a PSoC Emulator into Your Board
Ordering Code Definitions
Ordering Information
Sawn QFN
Orig. Submission Description of Change Date
Document History
Worldwide Sales and Design Support Products PSoC Solutions
Sales, Solutions, and Legal Information
USB