Cypress CY8C24123A manual DC Electrical Characteristics, DC Chip-Level Specifications

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CY8C24123A

CY8C24223A, CY8C24423A

DC Electrical Characteristics

DC Chip-Level Specifications

Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

Table 14. DC Chip-Level Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

Vdd

Supply Voltage

2.4

–

5.25

V

See DC POR and LVD specifications,

 

 

 

 

 

 

Table 29 on page 30.

IDD

Supply Current

–

5

8

mA

Conditions are Vdd = 5.0V, TA = 25°C,

 

 

 

 

 

 

CPU = 3 MHz, SYSCLK doubler

 

 

 

 

 

 

disabled, VC1 = 1.5 MHz,

 

 

 

 

 

 

VC2 = 93.75 kHz, VC3 = 93.75 kHz,

 

 

 

 

 

 

analog power = off.

 

 

 

 

 

 

SLIMO mode = 0. IMO = 24 MHz.

IDD3

Supply Current

–

3.3

6.0

mA

Conditions are Vdd = 3.3V, TA= 25 °C,

 

 

 

 

 

 

CPU = 3 MHz, SYSCLK doubler

 

 

 

 

 

 

disabled, VC1 = 1.5 MHz,

 

 

 

 

 

 

VC2 = 93.75 kHz, VC3 = 93.75 kHz,

 

 

 

 

 

 

analog power = off. SLIMO mode = 0.

 

 

 

 

 

 

IMO = 24 MHz.

IDD27

Supply Current

–

2

4

mA

Conditions are Vdd = 2.7V, TA = 25°C,

 

 

 

 

 

 

CPU = 0.75 MHz, SYSCLK doubler

 

 

 

 

 

 

disabled, VC1 = 0.375 MHz,

 

 

 

 

 

 

VC2 = 23.44 kHz, VC3 = 0.09 kHz,

 

 

 

 

 

 

analog power = off. SLIMO mode = 1.

 

 

 

 

 

 

IMO = 6 MHz.

ISB

Sleep (Mode) Current with POR, LVD, Sleep

–

3

6.5

μA

Conditions are with internal slow

 

Timer, and WDT.a

 

 

 

 

speed oscillator, Vdd = 3.3V, -40°C ≤

 

 

 

 

 

 

TA ≤ 55°C, analog power = off.

ISBH

Sleep (Mode) Current with POR, LVD, Sleep

–

4

25

μA

Conditions are with internal slow

 

Timer, and WDT at high temperature.a

 

 

 

 

speed oscillator, Vdd = 3.3V, 55°C < TA

 

 

 

 

 

 

≤ 85°C, analog power = off.

ISBXTL

Sleep (Mode) Current with POR, LVD, Sleep

–

4

7.5

μA

Conditions are with properly loaded,

 

Timer, WDT, and external crystal.a

 

 

 

 

1 μW max, 32.768 kHz crystal.

 

 

 

 

 

 

Vdd = 3.3V, -40°C ≤ TA ≤ 55°C, analog

 

 

 

 

 

 

power = off.

ISBXTLH

Sleep (Mode) Current with POR, LVD, Sleep

–

5

26

μA

Conditions are with properly loaded,

 

Timer, WDT, and external crystal at high

 

 

 

 

1μW max, 32.768 kHz crystal.

 

temperature.a

 

 

 

 

Vdd = 3.3 V, 55°C < T ≤ 85°C, analog

 

 

 

 

 

 

A

 

 

 

 

 

 

power = off.

VREF

Reference Voltage (Bandgap)

1.28

1.30

1.33

V

Trimmed for appropriate Vdd.

 

 

 

 

 

 

Vdd > 3.0V

VREF27

Reference Voltage (Bandgap)

1.16

1.30

1.33

V

Trimmed for appropriate Vdd.

 

 

 

 

 

 

Vdd = 2.4V to 3.0V

a.Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar functions enabled.

Document Number: 38-12028 Rev. *I

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Digital System PSoC Functional OverviewPSoC Core Analog System Block Diagram Analog SystemPSoC Device Characteristics PSoC Part Getting StartedAdditional System Resources Consultants Technical Support Application NotesDevelopment Tools PSoC Designer Software SubsystemsDevice Editor Design BrowserDesigning with User Modules Hardware ToolsDevice Editor Application EditorDocument Conventions Acronyms UsedUnits of Measure Numeric NamingPinouts Pin Part Pinoutt2PDIP 3SOICPin Part Pinout Pin Definitions 20-Pin PDIP, SSOP, and SoicSCL, ISSP-SCLK SDA, ISSP-SDATAActive High External Reset with Internal CY8C24423A 28-Pin PSoC DeviceSwitch Mode Pump SMP Connection Pin Definitions 32-Pin QFNTo External Components required ExtclkOCD Not for ProductionOCD Hclk OCD CclkRegister Reference Register ConventionsRegister Mapping Tables Abbreviations UsedName Addr Access Hex Register Map Bank 0 Table User SpaceRegister Map Bank 1 Table Configuration Space ACB01CR2 Cpuf CPUSCR1 CPUSCR0 Electrical Specifications Units of Measure Symbol Unit of MeasureOperating Temperature Absolute Maximum Ratings Symbol Description Min Typ UnitsOperating Temperature Symbol Description Min Typ Max Units Absolute Maximum RatingsDC Electrical Characteristics DC Chip-Level SpecificationsDC General Purpose IO Specifications DC Operational Amplifier Specifications Psrr OAAverage Input Offset Voltage Drift DC Low Power Comparator Specifications Low power comparator LPC reference Vdd Voltage rangeLPC supply current LPC voltage offset Document Number 38-12028 Rev. *IDC Analog Output Buffer Specifications Psrr OBDC Switch Mode Pump Specifications Output Voltage Ripple depends on Switching Frequency MHzSwitching Duty Cycle DC Analog Reference Specifications Bandgap Voltage Reference Agnd = Vdd/2Agnd = 2 x BandGap BG + Agnd = P24 P24 = Vdd/2 Agnd = 2 x BandGap Not Allowed Agnd = P24 P24 = Vdd/2CY8C24123A CY8C24223A, CY8C24423A DC Analog PSoC Block Specifications DC POR, SMP, and LVD SpecificationsDC Programming Specifications DC24M AC Electrical CharacteristicsAC Chip-Level Specifications MHz Refer to the AC Digital Block Nominal Specifications CPU Frequency 2.7V NominalDC12M MHz Duty Cycle Jitter12M1P MHz Period Jitter IMO32K Select EnableGain AC General Purpose IO Specifications AC Operational Amplifier Specifications Noise at 1 kHz Power = Medium, Opamp Bias = HighBW OA NV/rt-HzCY8C24123A CY8C24223A, CY8C24423A Typical Agnd Noise with P24 Bypass AC Low Power Comparator Specifications AC Digital Block SpecificationsCrcprs SpimPRS CRCBW OB AC Analog Output Buffer SpecificationsLarge Signal Bandwidth, 1V pp, 3dB BW, 100 pF Load AC External Clock Specifications AC Programming Specifications AC I2C SpecificationsPulse Width of spikes are suppressed by Input filter Setup Time for Stop ConditionBus Free Time Between a Stop and Start Condition Packaging Dimensions Packaging InformationPin 150-Mil Soic Pin 210-Mil Ssop 51-85014 *D Pin 5x5 mm QFN Pin Sawn QFN Package Capacitance on Crystal Pins Solder Reflow Peak TemperatureTypical Package Capacitance on Crystal Pins Thermal ImpedancesDevelopment Tool Selection SoftwareDevelopment Kits Evaluation ToolsAccessories Emulation and Programming Emulation and Programming AccessoriesDevice Programmers Third Party Tools Build a PSoC Emulator into Your BoardSawn QFN Ordering InformationOrdering Code Definitions Document History Orig. Submission Description of Change DateUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions

CY8C24123A specifications

The Cypress CY8C24123A is a prominent member of the PSoC (Programmable System-on-Chip) family, which integrates a microcontroller with programmable analog and digital components on a single chip. Designed for low-power applications, the CY8C24123A offers a compelling mix of features and technologies that make it a popular choice for embedded system developers.

One of the standout features of the CY8C24123A is its low power consumption, which allows it to extend battery life in portable applications. It operates at a voltage range of 1.71V to 5.5V, making it versatile for various power supply options. This device is equipped with a 24 MHz CPU that efficiently executes tasks while keeping energy usage minimal.

The chip boasts a rich set of programmable peripherals, including analog components such as operational amplifiers, comparators, and DACs, enabling designers to create custom signal processing pathways. These features are complemented by a variety of digital peripherals, like timers, UART, I2C, and SPI interfaces, which facilitate communication with other devices and microcontrollers. The integration of these components reduces the need for external components, leading to a more compact design and lower overall system costs.

Moreover, the CY8C24123A includes Flash memory (up to 2 KB) and SRAM (256 bytes), providing ample storage for application code and data. This Flash memory is reprogrammable, enabling developers to update their applications easily without needing to replace the chip.

Another defining characteristic of the CY8C24123A is its programmability. The device can be configured and programmed using the Cypress PSoC Designer software, which allows developers to design and simulate their applications in a user-friendly environment. The combination of hardware-based flexibility and software configuration provides a robust platform for creating custom solutions tailored to specific application requirements.

Overall, the Cypress CY8C24123A stands out for its balance of performance, programmability, and power efficiency. Its integration of programmable analog and digital blocks makes it suitable for a wide range of applications, including industrial control, consumer electronics, and automotive systems. The ability to customize the chip's functionality further boosts its appeal, making it an excellent choice for developers seeking a versatile and efficient solution for their embedded projects.
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