Cypress CY8C24123A manual AC External Clock Specifications

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CY8C24123A

CY8C24223A, CY8C24423A

Table 43. 2.7V AC Analog Output Buffer Specifications

Symbol	Description	Min	Typ	Max	Units
TROB	Rising Settling Time to 0.1%, 1V Step, 100 pF Load	–	–	4	μs
	Power = Low	–	–	4	μs
	Power = High	–	–	4	μs
TSOB	Falling Settling Time to 0.1%, 1V Step, 100 pF Load	–	–	3	μs
	Power = Low	–	–	3	μs
	Power = High	–	–	3	μs
SRROB	Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load	0.4	–	–	V/μs
	Power = Low	0.4	–	–	V/μs
	Power = High	0.4	–	–	V/μs
SRFOB	Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load	0.4	–	–	V/μs
	Power = Low	0.4	–	–	V/μs
	Power = High	0.4	–	–	V/μs
BWOB	Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load	0.6	–	–	MHz
	Power = Low	0.6	–	–	MHz
	Power = High	0.6	–	–	MHz
BWOB	Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load	180	–	–	kHz
	Power = Low	180	–	–	kHz
	Power = High	180	–	–	kHz

AC External Clock Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

Table 44. 5V AC External Clock Specifications

Symbol	Description	Min	Typ		Max	Units
FOSCEXT	Frequency	0.093	–		24.6	MHz
–	High Period	20.6	–		5300	ns

–	Low Period	20.6	–		–	ns

–	Power Up IMO to Switch	150	–		–	μs

Table 45. 3.3V AC External Clock Specifications

Symbol	Description	Min	Typ		Max	Units
FOSCEXT	Frequency with CPU Clock divide by 1a	0.093	–		12.3	MHz
FOSCEXT	Frequency with CPU Clock divide by 2 or greaterb	0.186	–		24.6	MHz
–	High Period with CPU Clock divide by 1	41.7	–		5300	ns

–	Low Period with CPU Clock divide by 1	41.7	–		–	ns

–	Power Up IMO to Switch	150	–		–	μs

a.Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.

b.If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met.

Document Number: 38-12028 Rev. *I

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Contents Features Logic Block DiagramCypress Semiconductor Corporation 198 Champion Court PSoC Functional Overview PSoC CoreDigital System Analog System Block Diagram Analog SystemAdditional System Resources PSoC Device Characteristics PSoC PartGetting Started Consultants Technical Support Application NotesDevice Editor Development ToolsPSoC Designer Software Subsystems Design BrowserDevice Editor Designing with User ModulesHardware Tools Application EditorUnits of Measure Document ConventionsAcronyms Used Numeric Naming2PDIP PinoutsPin Part Pinoutt 3SOICSCL, ISSP-SCLK Pin Part PinoutPin Definitions 20-Pin PDIP, SSOP, and Soic SDA, ISSP-SDATAActive High External Reset with Internal CY8C24423A 28-Pin PSoC DeviceTo External Components required Switch Mode Pump SMP ConnectionPin Definitions 32-Pin QFN ExtclkOCD Not for ProductionOCD Hclk OCD CclkRegister Mapping Tables Register ReferenceRegister Conventions Abbreviations UsedName Addr Access Hex Register Map Bank 0 Table User SpaceRegister Map Bank 1 Table Configuration Space ACB01CR2 Cpuf CPUSCR1 CPUSCR0 Electrical Specifications Units of Measure Symbol Unit of MeasureOperating Temperature Symbol Description Min Typ Max Units Operating TemperatureAbsolute Maximum Ratings Symbol Description Min Typ Units Absolute Maximum RatingsDC Electrical Characteristics DC Chip-Level SpecificationsDC General Purpose IO Specifications DC Operational Amplifier Specifications Psrr OAAverage Input Offset Voltage Drift LPC supply current DC Low Power Comparator SpecificationsLow power comparator LPC reference Vdd Voltage range LPC voltage offset Document Number 38-12028 Rev. *IDC Analog Output Buffer Specifications Psrr OBDC Switch Mode Pump Specifications Switching Frequency MHz Switching Duty CycleOutput Voltage Ripple depends on Agnd = 2 x BandGap BG + Agnd = P24 P24 = Vdd/2 DC Analog Reference SpecificationsBandgap Voltage Reference Agnd = Vdd/2 Agnd = 2 x BandGap Not Allowed Agnd = P24 P24 = Vdd/2CY8C24123A CY8C24223A, CY8C24423A DC Analog PSoC Block Specifications DC POR, SMP, and LVD SpecificationsDC Programming Specifications AC Electrical Characteristics AC Chip-Level SpecificationsDC24M DC12M MHz Refer to the AC Digital Block Nominal SpecificationsCPU Frequency 2.7V Nominal MHz Duty Cycle Jitter12M1P MHz Period Jitter IMOEnable Gain32K Select AC General Purpose IO Specifications BW OA AC Operational Amplifier SpecificationsNoise at 1 kHz Power = Medium, Opamp Bias = High NV/rt-HzCY8C24123A CY8C24223A, CY8C24423A Typical Agnd Noise with P24 Bypass Crcprs AC Low Power Comparator Specifications AC Digital Block Specifications SpimPRS CRCAC Analog Output Buffer Specifications Large Signal Bandwidth, 1V pp, 3dB BW, 100 pF LoadBW OB AC External Clock Specifications AC Programming Specifications AC I2C SpecificationsSetup Time for Stop Condition Bus Free Time Between a Stop and Start ConditionPulse Width of spikes are suppressed by Input filter Packaging Dimensions Packaging InformationPin 150-Mil Soic Pin 210-Mil Ssop 51-85014 *D Pin 5x5 mm QFN Pin Sawn QFN Package Typical Package Capacitance on Crystal Pins Capacitance on Crystal PinsSolder Reflow Peak Temperature Thermal ImpedancesDevelopment Kits Development Tool SelectionSoftware Evaluation ToolsDevice Programmers Accessories Emulation and ProgrammingEmulation and Programming Accessories Third Party Tools Build a PSoC Emulator into Your BoardOrdering Information Ordering Code DefinitionsSawn QFN Document History Orig. Submission Description of Change DateSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB