Cypress CY8C24123A manual Typical Agnd Noise with P24 Bypass

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CY8C24123A

CY8C24223A, CY8C24423A

When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.

Figure 20. Typical AGND Noise with P2[4] Bypass

dBV/rtHz

 

 

 

 

 

 

10000

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

0.01

 

 

 

 

 

 

0.1

 

 

 

 

 

 

1.0

 

 

 

 

 

 

10

1000

 

 

 

 

 

 

100

 

 

 

 

 

 

0.001

0.01

0.1

Freq (kHz)

1

10

100

At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level.

Figure 21. Typical Opamp Noise

nV/rtHz

 

 

 

 

 

 

10000

 

 

 

 

 

PH_BH

 

 

 

 

 

 

 

 

 

 

 

 

PH_BL

 

 

 

 

 

 

PM_BL

 

 

 

 

 

 

PL_BL

1000

 

 

 

 

 

 

100

 

 

 

 

 

 

10

 

 

 

 

 

 

0.001

0.01

0.1

Freq (kHz)

1

10

100

Document Number: 38-12028 Rev. *I

Page 38 of 56

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Digital System PSoC Functional OverviewPSoC Core Analog System Block Diagram Analog SystemAdditional System Resources PSoC Device Characteristics PSoC PartGetting Started Consultants Technical Support Application NotesDevice Editor Development ToolsPSoC Designer Software Subsystems Design BrowserDevice Editor Designing with User ModulesHardware Tools Application EditorUnits of Measure Document ConventionsAcronyms Used Numeric Naming2PDIP PinoutsPin Part Pinoutt 3SOICSCL, ISSP-SCLK Pin Part PinoutPin Definitions 20-Pin PDIP, SSOP, and Soic SDA, ISSP-SDATAActive High External Reset with Internal CY8C24423A 28-Pin PSoC DeviceTo External Components required Switch Mode Pump SMP ConnectionPin Definitions 32-Pin QFN ExtclkOCD Not for ProductionOCD Hclk OCD CclkRegister Mapping Tables Register ReferenceRegister Conventions Abbreviations UsedName Addr Access Hex Register Map Bank 0 Table User SpaceRegister Map Bank 1 Table Configuration Space ACB01CR2 Cpuf CPUSCR1 CPUSCR0 Electrical Specifications Units of Measure Symbol Unit of MeasureOperating Temperature Symbol Description Min Typ Max Units Operating TemperatureAbsolute Maximum Ratings Symbol Description Min Typ Units Absolute Maximum RatingsDC Electrical Characteristics DC Chip-Level SpecificationsDC General Purpose IO Specifications DC Operational Amplifier Specifications Psrr OAAverage Input Offset Voltage Drift LPC supply current DC Low Power Comparator SpecificationsLow power comparator LPC reference Vdd Voltage range LPC voltage offset Document Number 38-12028 Rev. *IDC Analog Output Buffer Specifications Psrr OBDC Switch Mode Pump Specifications Output Voltage Ripple depends on Switching Frequency MHzSwitching Duty Cycle Agnd = 2 x BandGap BG + Agnd = P24 P24 = Vdd/2 DC Analog Reference SpecificationsBandgap Voltage Reference Agnd = Vdd/2 Agnd = 2 x BandGap Not Allowed Agnd = P24 P24 = Vdd/2CY8C24123A CY8C24223A, CY8C24423A DC Analog PSoC Block Specifications DC POR, SMP, and LVD SpecificationsDC Programming Specifications DC24M AC Electrical CharacteristicsAC Chip-Level Specifications DC12M MHz Refer to the AC Digital Block Nominal SpecificationsCPU Frequency 2.7V Nominal MHz Duty Cycle Jitter12M1P MHz Period Jitter IMO32K Select EnableGain AC General Purpose IO Specifications BW OA AC Operational Amplifier SpecificationsNoise at 1 kHz Power = Medium, Opamp Bias = High NV/rt-HzCY8C24123A CY8C24223A, CY8C24423A Typical Agnd Noise with P24 Bypass Crcprs AC Low Power Comparator SpecificationsAC Digital Block Specifications SpimPRS CRCBW OB AC Analog Output Buffer SpecificationsLarge Signal Bandwidth, 1V pp, 3dB BW, 100 pF Load AC External Clock Specifications AC Programming Specifications AC I2C SpecificationsPulse Width of spikes are suppressed by Input filter Setup Time for Stop ConditionBus Free Time Between a Stop and Start Condition Packaging Dimensions Packaging InformationPin 150-Mil Soic Pin 210-Mil Ssop 51-85014 *D Pin 5x5 mm QFN Pin Sawn QFN Package Typical Package Capacitance on Crystal Pins Capacitance on Crystal PinsSolder Reflow Peak Temperature Thermal ImpedancesDevelopment Kits Development Tool SelectionSoftware Evaluation ToolsDevice Programmers Accessories Emulation and ProgrammingEmulation and Programming Accessories Third Party Tools Build a PSoC Emulator into Your BoardSawn QFN Ordering InformationOrdering Code Definitions Document History Orig. Submission Description of Change DateUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions

CY8C24123A specifications

The Cypress CY8C24123A is a prominent member of the PSoC (Programmable System-on-Chip) family, which integrates a microcontroller with programmable analog and digital components on a single chip. Designed for low-power applications, the CY8C24123A offers a compelling mix of features and technologies that make it a popular choice for embedded system developers.

One of the standout features of the CY8C24123A is its low power consumption, which allows it to extend battery life in portable applications. It operates at a voltage range of 1.71V to 5.5V, making it versatile for various power supply options. This device is equipped with a 24 MHz CPU that efficiently executes tasks while keeping energy usage minimal.

The chip boasts a rich set of programmable peripherals, including analog components such as operational amplifiers, comparators, and DACs, enabling designers to create custom signal processing pathways. These features are complemented by a variety of digital peripherals, like timers, UART, I2C, and SPI interfaces, which facilitate communication with other devices and microcontrollers. The integration of these components reduces the need for external components, leading to a more compact design and lower overall system costs.

Moreover, the CY8C24123A includes Flash memory (up to 2 KB) and SRAM (256 bytes), providing ample storage for application code and data. This Flash memory is reprogrammable, enabling developers to update their applications easily without needing to replace the chip.

Another defining characteristic of the CY8C24123A is its programmability. The device can be configured and programmed using the Cypress PSoC Designer software, which allows developers to design and simulate their applications in a user-friendly environment. The combination of hardware-based flexibility and software configuration provides a robust platform for creating custom solutions tailored to specific application requirements.

Overall, the Cypress CY8C24123A stands out for its balance of performance, programmability, and power efficiency. Its integration of programmable analog and digital blocks makes it suitable for a wide range of applications, including industrial control, consumer electronics, and automotive systems. The ability to customize the chip's functionality further boosts its appeal, making it an excellent choice for developers seeking a versatile and efficient solution for their embedded projects.