Cypress CY8C24123A Designing with User Modules, Hardware Tools, Device Editor, Application Editor

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CY8C24123A CY8C24223A, CY8C24423A

Debugger

The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.

Online Help System

The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices.

The emulator consists of a base unit that connects to the PC through the parallel or USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.

Designing with User Modules

The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, can implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware and the software. This substantially lowers the risk of having to select a different part to meet the final design requirements.

To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called “User Modules.” User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other uncommon peripherals, such as DTMF Generators and Bi-Quad analog filter sections.

Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to

establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides high-level functions to control and respond to hardware events at run-time. The API also provides optional interrupt service routines that you can adapt as needed.

The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module.

The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. Pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you can also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides high-level user module API functions.

Figure 4. User Module and Source Code Development Flows

 

 

Device Editor

 

 

 

 

 

 

 

 

 

 

User

 

Placement

 

Source

 

 

 

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Module

 

 

Code

 

 

 

Parameter-

 

 

 

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Generator

 

 

 

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Generate

Application

Application Editor

Project

 

Source

 

Build

 

Code

 

Manager

 

 

Manager

 

Editor

 

 

 

 

 

 

 

 

 

 

 

 

 

Build

 

 

 

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Debugger

 

 

 

 

 

 

 

 

 

 

Interface

 

Storage

 

Event &

 

 

 

 

Breakpoint

 

 

to ICE

 

Inspector

 

 

 

 

 

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Document Number: 38-12028 Rev. *I

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Contents Features Logic Block DiagramCypress Semiconductor Corporation 198 Champion Court PSoC Functional Overview PSoC CoreDigital System Analog System Block Diagram Analog SystemAdditional System Resources PSoC Device Characteristics PSoC PartGetting Started Consultants Technical Support Application NotesDevice Editor Development ToolsPSoC Designer Software Subsystems Design BrowserDevice Editor Designing with User ModulesHardware Tools Application EditorUnits of Measure Document ConventionsAcronyms Used Numeric Naming2PDIP PinoutsPin Part Pinoutt 3SOICSCL, ISSP-SCLK Pin Part PinoutPin Definitions 20-Pin PDIP, SSOP, and Soic SDA, ISSP-SDATAActive High External Reset with Internal CY8C24423A 28-Pin PSoC DeviceTo External Components required Switch Mode Pump SMP ConnectionPin Definitions 32-Pin QFN ExtclkOCD Not for ProductionOCD Hclk OCD CclkRegister Mapping Tables Register ReferenceRegister Conventions Abbreviations UsedName Addr Access Hex Register Map Bank 0 Table User SpaceRegister Map Bank 1 Table Configuration Space ACB01CR2 Cpuf CPUSCR1 CPUSCR0 Electrical Specifications Units of Measure Symbol Unit of MeasureOperating Temperature Symbol Description Min Typ Max Units Operating TemperatureAbsolute Maximum Ratings Symbol Description Min Typ Units Absolute Maximum RatingsDC Electrical Characteristics DC Chip-Level SpecificationsDC General Purpose IO Specifications DC Operational Amplifier Specifications Psrr OAAverage Input Offset Voltage Drift LPC supply current DC Low Power Comparator SpecificationsLow power comparator LPC reference Vdd Voltage range LPC voltage offset Document Number 38-12028 Rev. *IDC Analog Output Buffer Specifications Psrr OBDC Switch Mode Pump Specifications Switching Frequency MHz Switching Duty CycleOutput Voltage Ripple depends on Agnd = 2 x BandGap BG + Agnd = P24 P24 = Vdd/2 DC Analog Reference SpecificationsBandgap Voltage Reference Agnd = Vdd/2 Agnd = 2 x BandGap Not Allowed Agnd = P24 P24 = Vdd/2CY8C24123A CY8C24223A, CY8C24423A DC Analog PSoC Block Specifications DC POR, SMP, and LVD SpecificationsDC Programming Specifications AC Electrical Characteristics AC Chip-Level SpecificationsDC24M DC12M MHz Refer to the AC Digital Block Nominal SpecificationsCPU Frequency 2.7V Nominal MHz Duty Cycle Jitter12M1P MHz Period Jitter IMOEnable Gain32K Select AC General Purpose IO Specifications BW OA AC Operational Amplifier SpecificationsNoise at 1 kHz Power = Medium, Opamp Bias = High NV/rt-HzCY8C24123A CY8C24223A, CY8C24423A Typical Agnd Noise with P24 Bypass Crcprs AC Low Power Comparator SpecificationsAC Digital Block Specifications SpimPRS CRCAC Analog Output Buffer Specifications Large Signal Bandwidth, 1V pp, 3dB BW, 100 pF LoadBW OB AC External Clock Specifications AC Programming Specifications AC I2C SpecificationsSetup Time for Stop Condition Bus Free Time Between a Stop and Start ConditionPulse Width of spikes are suppressed by Input filter Packaging Dimensions Packaging InformationPin 150-Mil Soic Pin 210-Mil Ssop 51-85014 *D Pin 5x5 mm QFN Pin Sawn QFN Package Typical Package Capacitance on Crystal Pins Capacitance on Crystal PinsSolder Reflow Peak Temperature Thermal ImpedancesDevelopment Kits Development Tool SelectionSoftware Evaluation ToolsDevice Programmers Accessories Emulation and ProgrammingEmulation and Programming Accessories Third Party Tools Build a PSoC Emulator into Your BoardOrdering Information Ordering Code DefinitionsSawn QFN Document History Orig. Submission Description of Change DateSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB

CY8C24123A specifications

The Cypress CY8C24123A is a prominent member of the PSoC (Programmable System-on-Chip) family, which integrates a microcontroller with programmable analog and digital components on a single chip. Designed for low-power applications, the CY8C24123A offers a compelling mix of features and technologies that make it a popular choice for embedded system developers.

One of the standout features of the CY8C24123A is its low power consumption, which allows it to extend battery life in portable applications. It operates at a voltage range of 1.71V to 5.5V, making it versatile for various power supply options. This device is equipped with a 24 MHz CPU that efficiently executes tasks while keeping energy usage minimal.

The chip boasts a rich set of programmable peripherals, including analog components such as operational amplifiers, comparators, and DACs, enabling designers to create custom signal processing pathways. These features are complemented by a variety of digital peripherals, like timers, UART, I2C, and SPI interfaces, which facilitate communication with other devices and microcontrollers. The integration of these components reduces the need for external components, leading to a more compact design and lower overall system costs.

Moreover, the CY8C24123A includes Flash memory (up to 2 KB) and SRAM (256 bytes), providing ample storage for application code and data. This Flash memory is reprogrammable, enabling developers to update their applications easily without needing to replace the chip.

Another defining characteristic of the CY8C24123A is its programmability. The device can be configured and programmed using the Cypress PSoC Designer software, which allows developers to design and simulate their applications in a user-friendly environment. The combination of hardware-based flexibility and software configuration provides a robust platform for creating custom solutions tailored to specific application requirements.

Overall, the Cypress CY8C24123A stands out for its balance of performance, programmability, and power efficiency. Its integration of programmable analog and digital blocks makes it suitable for a wide range of applications, including industrial control, consumer electronics, and automotive systems. The ability to customize the chip's functionality further boosts its appeal, making it an excellent choice for developers seeking a versatile and efficient solution for their embedded projects.