Cypress CY8C24123A manual Prs, Crc

CY8C24123A

CY8C24223A, CY8C24423A

Table 40. 2.7V AC Digital Block Specifications

Function	Description	Min	Typ	Max	Units	Notes
All	Maximum Block Clocking Frequency			12.7	MHz	2.4V < Vdd < 3.0V
Functions
Timer	Capture Pulse Width	100a	–0	–0	ns
	Maximum Frequency, With or Without Capture	–	–	12.7	MHz
Counter	Enable Pulse Width	100a	–0	–0	ns
	Maximum Frequency, No Enable Input	–	–	12.7	MHz
	Maximum Frequency, Enable Input	–	–	12.7	MHz
Dead	Kill Pulse Width:
Band
	Asynchronous Restart Mode	20	–	–	ns
	Synchronous Restart Mode	100a	–0	–0	ns
	Disable Mode0	100a	–0	–0	ns
	Maximum Frequency	–	–	12.7	MHz
CRCPRS	Maximum Input Clock Frequency	–	–	12.7	MHz
(PRS
Mode)
CRCPRS	Maximum Input Clock Frequency	–	–	12.7	MHz
(CRC
Mode)
SPIM	Maximum Input Clock Frequency	–	–	6.35	MHz	Maximum data rate at 3.17 MHz
						due to 2 x over clocking.
SPIS	Maximum Input Clock Frequency	–	–	4.23	ns
	Width of SS_ Negated Between Transmissions	100a	–0	–0	ns
Trans-	Maximum Input Clock Frequency	–	–	12.7	MHz	Maximum data rate at 1.59 MHz
mitter						due to 8 x over clocking.
Receiver	Maximum Input Clock Frequency	–	–	12.7	MHz	Maximum data rate at 1.59 MHz
						due to 8 x over clocking.

a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).

Document Number: 38-12028 Rev. *I Page 40 of 56

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