Cypress CY8C24123A manual DC Programming Specifications

Page 31

CY8C24123A

CY8C24223A, CY8C24423A

DC Programming Specifications

Table 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

Table 30. DC Programming Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

VddIWRIT

Supply Voltage for Flash Write Operations

2.70

–

–

V

 

E

 

 

 

 

 

 

IDDP

Supply Current During Programming or Verify

–

5

25

mA

 

VILP

Input Low Voltage During Programming or Verify

–

–

0.8

V

 

VIHP

Input High Voltage During Programming or Verify

2.1

–

–

V

 

IILP

Input Current when Applying Vilp to P1[0] or P1[1]

–

–

0.2

mA

Driving internal pull down

 

During Programming or Verify

 

 

 

 

resistor.

IIHP

Input Current when Applying Vihp to P1[0] or P1[1]

–

–

1.5

mA

Driving internal pull down

 

During Programming or Verify

 

 

 

 

resistor.

VOLV

Output Low Voltage During Programming or Verify

–

–

Vss + 0.75

V

 

VOHV

Output High Voltage During Programming or

Vdd - 1.0

–

Vdd

V

 

 

Verify

 

 

 

 

 

FlashENP

Flash Endurance (per block)

50,000

–

–

–

Erase/write cycles per

B

 

 

 

 

 

block

FlashENT

Flash Endurance (total)a

1,800,000

–

–

–

Erase/write cycles

FlashDR

Flash Data Retention

10

–

–

Years

 

a.A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles).

For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

Document Number: 38-12028 Rev. *I

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Contents Logic Block Diagram FeaturesCypress Semiconductor Corporation 198 Champion Court PSoC Core PSoC Functional OverviewDigital System Analog System Analog System Block DiagramConsultants Technical Support Application Notes PSoC Device Characteristics PSoC PartGetting Started Additional System ResourcesDesign Browser Development ToolsPSoC Designer Software Subsystems Device EditorApplication Editor Designing with User ModulesHardware Tools Device EditorNumeric Naming Document ConventionsAcronyms Used Units of Measure3SOIC PinoutsPin Part Pinoutt 2PDIPSDA, ISSP-SDATA Pin Part PinoutPin Definitions 20-Pin PDIP, SSOP, and Soic SCL, ISSP-SCLKCY8C24423A 28-Pin PSoC Device Active High External Reset with InternalExtclk Switch Mode Pump SMP ConnectionPin Definitions 32-Pin QFN To External Components requiredNot for Production OCDOCD Cclk OCD HclkAbbreviations Used Register ReferenceRegister Conventions Register Mapping TablesRegister Map Bank 0 Table User Space Name Addr Access HexRegister Map Bank 1 Table Configuration Space ACB01CR2 Cpuf CPUSCR1 CPUSCR0 Units of Measure Symbol Unit of Measure Electrical SpecificationsAbsolute Maximum Ratings Operating TemperatureAbsolute Maximum Ratings Symbol Description Min Typ Units Operating Temperature Symbol Description Min Typ Max UnitsDC Chip-Level Specifications DC Electrical CharacteristicsDC General Purpose IO Specifications Psrr OA DC Operational Amplifier SpecificationsAverage Input Offset Voltage Drift LPC voltage offset Document Number 38-12028 Rev. *I DC Low Power Comparator SpecificationsLow power comparator LPC reference Vdd Voltage range LPC supply currentPsrr OB DC Analog Output Buffer SpecificationsDC Switch Mode Pump Specifications Switching Duty Cycle Switching Frequency MHzOutput Voltage Ripple depends on Agnd = 2 x BandGap Not Allowed Agnd = P24 P24 = Vdd/2 DC Analog Reference Specifications Bandgap Voltage Reference Agnd = Vdd/2 Agnd = 2 x BandGap BG + Agnd = P24 P24 = Vdd/2CY8C24123A CY8C24223A, CY8C24423A DC POR, SMP, and LVD Specifications DC Analog PSoC Block SpecificationsDC Programming Specifications AC Chip-Level Specifications AC Electrical CharacteristicsDC24M MHz Duty Cycle Jitter12M1P MHz Period Jitter IMO MHz Refer to the AC Digital Block Nominal SpecificationsCPU Frequency 2.7V Nominal DC12MGain Enable32K Select AC General Purpose IO Specifications NV/rt-Hz AC Operational Amplifier SpecificationsNoise at 1 kHz Power = Medium, Opamp Bias = High BW OACY8C24123A CY8C24223A, CY8C24423A Typical Agnd Noise with P24 Bypass Spim AC Low Power Comparator SpecificationsAC Digital Block Specifications CrcprsCRC PRSLarge Signal Bandwidth, 1V pp, 3dB BW, 100 pF Load AC Analog Output Buffer SpecificationsBW OB AC External Clock Specifications AC I2C Specifications AC Programming SpecificationsBus Free Time Between a Stop and Start Condition Setup Time for Stop ConditionPulse Width of spikes are suppressed by Input filter Packaging Information Packaging DimensionsPin 150-Mil Soic Pin 210-Mil Ssop 51-85014 *D Pin 5x5 mm QFN Pin Sawn QFN Package Thermal Impedances Capacitance on Crystal PinsSolder Reflow Peak Temperature Typical Package Capacitance on Crystal PinsEvaluation Tools Development Tool SelectionSoftware Development KitsThird Party Tools Build a PSoC Emulator into Your Board Accessories Emulation and ProgrammingEmulation and Programming Accessories Device ProgrammersOrdering Code Definitions Ordering InformationSawn QFN Orig. Submission Description of Change Date Document HistoryWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB
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