Cypress CY8C24123A manual Features, Logic Block Diagram

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CY8C24123A

CY8C24223A, CY8C24423A

PSoC® Programmable System-on-Chip™

Features

■Powerful Harvard Architecture Processor

❐M8C Processor Speeds to 24 MHz

❐8x8 Multiply, 32-Bit Accumulate

❐Low Power at High Speed

❐2.4 to 5.25V Operating Voltage

❐Operating Voltages Down to 1.0V Using On-Chip Switch Mode Pump (SMP)

❐Industrial Temperature Range: -40°C to +85°C

■Advanced Peripherals (PSoC Blocks)

❐Six Rail-to-Rail Analog PSoC Blocks Provide:

•Up to 14-Bit ADCs

•Up to 9-Bit DACs

•Programmable Gain Amplifiers

•Programmable Filters and Comparators

■New CY8C24x23A PSoC Device

❐Derived From the CY8C24x23 Device

❐Low Power and Low Voltage (2.4V)

■Additional System Resources

❐I2C™ Slave, Master, and MultiMaster to 400 kHz

❐Watchdog and Sleep Timers

❐User-Configurable Low Voltage Detection

❐Integrated Supervisory Circuit

❐On-Chip Precision Voltage Reference

■Complete Development Tools

❐Free Development Software (PSoC Designer™)

❐Full-Featured, In-Circuit Emulator, and Programmer

❐Full Speed Emulation

❐Complex Breakpoint Structure

❐128K Trace Memory

❐Four Digital PSoC Blocks Provide:

•8 to 32-Bit Timers, Counters, and PWMs

•CRC and PRS Modules

•Full-Duplex UART

•Multiple SPI™ Masters or Slaves

•Connectable to All GPIO Pins

❐Complex Peripherals by Combining Blocks

■Precision, Programmable Clocking

❐Internal ±2.5% 24/48 MHz Oscillator

❐High accuracy 24 MHz with optional 32 kHz Crystal and PLL

❐Optional External Oscillator, up to 24 MHz

❐Internal Oscillator for Watchdog and Sleep

■Flexible On-Chip Memory

❐4K Flash Program Storage 50,000 Erase/Write Cycles

❐256 Bytes SRAM Data Storage

❐In-System Serial Programming (ISSP)

❐Partial Flash Updates

❐Flexible Protection Modes

❐EEPROM Emulation in Flash

■Programmable Pin Configurations

❐25 mA Sink on all GPIO

❐Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on All GPIO

❐Up to Ten Analog Inputs on GPIO

❐Two 30 mA Analog Outputs on GPIO

❐Configurable Interrupt on All GPIO

Logic Block Diagram

 

 

 

 

 

 

 

 

 

Analog

 

 

PSoC CORE

 

Port 2 Port 1

 

Port 0 Drivers

 

 

 

 

 

 

 

 

System Bus

 

 

 

 

 

 

Global Digital Interconnect

 

Global Analog Interconnect

 

 

 

 

 

SRAM

SROM

Flash 4K

 

 

 

 

256 Bytes

 

 

 

 

 

 

 

 

 

 

 

Interrupt

CPU Core (M8C)

Sleep and

 

 

 

 

 

Watchdog

 

 

Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

Multiple Clock Sources

 

 

 

 

(Includes IMO, ILO, PLL, and ECO)

 

DIGITAL SYSTEM

 

ANALOG SYSTEM

 

 

 

 

 

 

 

Analog

 

 

Digital

 

Analog

 

Ref

 

 

 

 

 

 

 

Block

 

Block

 

 

 

 

Array

 

Array

 

Analog

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

 

 

 

 

 

 

 

Muxing

 

Digital

Multiply

Decimator

I2C

POR and LVD

 

Internal

Switch

 

Voltage

Mode

Clocks

Accum.

 

 

System Resets

Ref.

Pump

 

 

 

 

 

 

 

 

SYSTEM RESOURCES

 

 

 

Cypress Semiconductor Corporation • 198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document Number: 38-12028 Rev. *I

 

Revised December 11, 2008

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Contents Logic Block Diagram FeaturesCypress Semiconductor Corporation 198 Champion Court PSoC Core PSoC Functional OverviewDigital System Analog System Analog System Block DiagramGetting Started PSoC Device Characteristics PSoC PartAdditional System Resources Consultants Technical Support Application NotesPSoC Designer Software Subsystems Development ToolsDevice Editor Design BrowserHardware Tools Designing with User ModulesDevice Editor Application EditorAcronyms Used Document ConventionsUnits of Measure Numeric NamingPin Part Pinoutt Pinouts2PDIP 3SOICPin Definitions 20-Pin PDIP, SSOP, and Soic Pin Part PinoutSCL, ISSP-SCLK SDA, ISSP-SDATACY8C24423A 28-Pin PSoC Device Active High External Reset with InternalPin Definitions 32-Pin QFN Switch Mode Pump SMP ConnectionTo External Components required ExtclkNot for Production OCDOCD Cclk OCD HclkRegister Conventions Register ReferenceRegister Mapping Tables Abbreviations UsedRegister Map Bank 0 Table User Space Name Addr Access HexRegister Map Bank 1 Table Configuration Space ACB01CR2 Cpuf CPUSCR1 CPUSCR0 Units of Measure Symbol Unit of Measure Electrical SpecificationsAbsolute Maximum Ratings Symbol Description Min Typ Units Operating TemperatureOperating Temperature Symbol Description Min Typ Max Units Absolute Maximum RatingsDC Chip-Level Specifications DC Electrical CharacteristicsDC General Purpose IO Specifications Psrr OA DC Operational Amplifier SpecificationsAverage Input Offset Voltage Drift Low power comparator LPC reference Vdd Voltage range DC Low Power Comparator SpecificationsLPC supply current LPC voltage offset Document Number 38-12028 Rev. *IPsrr OB DC Analog Output Buffer SpecificationsDC Switch Mode Pump Specifications Switching Duty Cycle Switching Frequency MHzOutput Voltage Ripple depends on Bandgap Voltage Reference Agnd = Vdd/2 DC Analog Reference SpecificationsAgnd = 2 x BandGap BG + Agnd = P24 P24 = Vdd/2 Agnd = 2 x BandGap Not Allowed Agnd = P24 P24 = Vdd/2CY8C24123A CY8C24223A, CY8C24423A DC POR, SMP, and LVD Specifications DC Analog PSoC Block SpecificationsDC Programming Specifications AC Chip-Level Specifications AC Electrical CharacteristicsDC24M CPU Frequency 2.7V Nominal MHz Refer to the AC Digital Block Nominal SpecificationsDC12M MHz Duty Cycle Jitter12M1P MHz Period Jitter IMOGain Enable32K Select AC General Purpose IO Specifications Noise at 1 kHz Power = Medium, Opamp Bias = High AC Operational Amplifier SpecificationsBW OA NV/rt-HzCY8C24123A CY8C24223A, CY8C24423A Typical Agnd Noise with P24 Bypass AC Digital Block Specifications AC Low Power Comparator SpecificationsCrcprs SpimCRC PRSLarge Signal Bandwidth, 1V pp, 3dB BW, 100 pF Load AC Analog Output Buffer SpecificationsBW OB AC External Clock Specifications AC I2C Specifications AC Programming SpecificationsBus Free Time Between a Stop and Start Condition Setup Time for Stop ConditionPulse Width of spikes are suppressed by Input filter Packaging Information Packaging DimensionsPin 150-Mil Soic Pin 210-Mil Ssop 51-85014 *D Pin 5x5 mm QFN Pin Sawn QFN Package Solder Reflow Peak Temperature Capacitance on Crystal PinsTypical Package Capacitance on Crystal Pins Thermal ImpedancesSoftware Development Tool SelectionDevelopment Kits Evaluation ToolsEmulation and Programming Accessories Accessories Emulation and ProgrammingDevice Programmers Third Party Tools Build a PSoC Emulator into Your BoardOrdering Code Definitions Ordering InformationSawn QFN Orig. Submission Description of Change Date Document HistoryWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB

CY8C24123A specifications

The Cypress CY8C24123A is a prominent member of the PSoC (Programmable System-on-Chip) family, which integrates a microcontroller with programmable analog and digital components on a single chip. Designed for low-power applications, the CY8C24123A offers a compelling mix of features and technologies that make it a popular choice for embedded system developers.

One of the standout features of the CY8C24123A is its low power consumption, which allows it to extend battery life in portable applications. It operates at a voltage range of 1.71V to 5.5V, making it versatile for various power supply options. This device is equipped with a 24 MHz CPU that efficiently executes tasks while keeping energy usage minimal.

The chip boasts a rich set of programmable peripherals, including analog components such as operational amplifiers, comparators, and DACs, enabling designers to create custom signal processing pathways. These features are complemented by a variety of digital peripherals, like timers, UART, I2C, and SPI interfaces, which facilitate communication with other devices and microcontrollers. The integration of these components reduces the need for external components, leading to a more compact design and lower overall system costs.

Moreover, the CY8C24123A includes Flash memory (up to 2 KB) and SRAM (256 bytes), providing ample storage for application code and data. This Flash memory is reprogrammable, enabling developers to update their applications easily without needing to replace the chip.

Another defining characteristic of the CY8C24123A is its programmability. The device can be configured and programmed using the Cypress PSoC Designer software, which allows developers to design and simulate their applications in a user-friendly environment. The combination of hardware-based flexibility and software configuration provides a robust platform for creating custom solutions tailored to specific application requirements.

Overall, the Cypress CY8C24123A stands out for its balance of performance, programmability, and power efficiency. Its integration of programmable analog and digital blocks makes it suitable for a wide range of applications, including industrial control, consumer electronics, and automotive systems. The ability to customize the chip's functionality further boosts its appeal, making it an excellent choice for developers seeking a versatile and efficient solution for their embedded projects.
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