Cypress CY8C24123A manual AC Programming Specifications, AC I2C Specifications

CY8C24123A

CY8C24223A, CY8C24423A

Table 46. 2.7V AC External Clock Specifications

Symbol	Description	Min	Typ	Max	Units
FOSCEXT	Frequency with CPU Clock divide by 1a	0.093	–	12.3	MHz
FOSCEXT	Frequency with CPU Clock divide by 2 or greaterb	0.186	–	12.3	MHz
–	High Period with CPU Clock divide by 1	41.7	–	5300	ns
–	Low Period with CPU Clock divide by 1	41.7	–	–	ns
–	Power Up IMO to Switch	150	–	–	μs

a.Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.

b.If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met.

AC Programming Specifications

Table 47 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

Table 47. AC Programming Specifications

Symbol	Description	Min	Typ	Max	Units	Notes
TRSCLK	Rise Time of SCLK	1	–	20	ns
TFSCLK	Fall Time of SCLK	1	–	20	ns
TSSCLK	Data Setup Time to Falling Edge of SCLK	40	–	–	ns
THSCLK	Data Hold Time from Falling Edge of SCLK	40	–	–	ns
FSCLK	Frequency of SCLK	0	–	8	MHz
TERASEB	Flash Erase Time (Block)	–	20	–	ms
TWRITE	Flash Block Write Time	–	20	–	ms
TDSCLK	Data Out Delay from Falling Edge of SCLK	–	–	45	ns	Vdd > 3.6
TDSCLK3	Data Out Delay from Falling Edge of SCLK	–	–	50	ns	3.0 ≤ Vdd ≤ 3.6
TDSCLK2	Data Out Delay from Falling Edge of SCLK	–	–	70	ns	2.4 ≤ Vdd ≤ 3.0

AC I2C Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

Table 48. AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V

Symbol	Description	Standard Mode		Fast Mode		Units
		Min	Max	Min	Max
FSCLI2C	SCL Clock Frequency	0	100	0	400	kHz
THDSTAI2C	Hold Time (repeated) START Condition. After	4.0	–	0.6	–	μs
	this period, the first clock pulse is generated.
TLOWI2C	LOW Period of the SCL Clock	4.7	–	1.3	–	μs
THIGHI2C	HIGH Period of the SCL Clock	4.0	–	0.6	–	μs
TSUSTAI2C	Setup Time for a Repeated START Condition	4.7	–	0.6	–	μs
THDDATI2C	Data Hold Time	0	–	0	–	μs
TSUDATI2C	Data Setup Time	250	–	100a	–	ns

Document Number: 38-12028 Rev. *I Page 43 of 56

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