Xilinx PCI-X v5.1 manual Conventions, Typographical, Preface About This Guide

Page 10

R

Preface: About This Guide

Conventions

Typographical

The following typographical conventions are used in this document:

	Convention	Meaning or Use	Example

		Messages, prompts, and
	Courier font	program files that the system	speed grade: - 100
		displays

	Courier bold	Literal commands you enter in	ngdbuild design_name
	Courier bold	a syntactical statement	ngdbuild design_name

		Variables in a syntax	<design_name>
	angle brackets < >	statement for which you must
		supply values

		References to other manuals	See the Initiator/Target User
		References to other manuals	Guide for more information.
			Guide for more information.

	Italic font		If a wire is drawn so that it
		Emphasis in text	overlaps the pin of a symbol,
		Emphasis in text	the two nets are not
			the two nets are not
			connected.

		An optional entry or
	Square brackets [ ]	parameter. However, in bus	ngdbuild [option_name]
	Square brackets [ ]	specifications, such as	design_name
		specifications, such as	design_name
		bus[7:0], they are required.

	Braces { }	A list of items from which you	lowpwr ={onoff}
	Braces { }	must choose one or more	lowpwr ={onoff}
		must choose one or more

	Vertical bar	Separates items in a list of	lowpwr ={onoff}
	Vertical bar	choices	lowpwr ={onoff}
		choices

	Vertical ellipsis		IOB #1: Name = QOUT’
	Vertical ellipsis	Repetitive material that has	IOB #2: Name = CLKIN’
	.		IOB #2: Name = CLKIN’
	.		.
	.	been omitted	.
	.	been omitted	.
	.		.
	.		.
			.

	Horizontal ellipsis . . .	Omitted repetitive material	allow block block_name
			loc1 loc2... locn;

10	www.xilinx.com	PCI-X v5.1 165 Getting Started Guide
		UG158 March 24, 2008

Image 10

Contents LogiCORE IP Initiator/Target v5.1 for PCI-X UG158 March 24PCI-X v5.1 165 Getting Started Guide UG158 March 24 Version RevisionUg000preface.fm to Guide Version Revision Table of Contents Implementing a Design Schedule of Figures 8Options for Implementation Options/ConstraintsPCI-X v5.1 165 Getting Started Guide Guide Contents About This GuidePreface About This Guide ConventionsTypographical Convention Meaning or Use ExampleOnline Document ConventionsPreface About This Guide System Requirements Getting StartedAbout the Example Design Feedback Additional DocumentationTechnical Support Core Interface for PCI-XLicensing Options Licensing the CoreBefore you Begin Full System Hardware EvaluationDirect Download Installing Your License FileFull License Licensing the CoreFamily Specific Considerations Design SupportSimulation Virtex-4 Devices Wrapper Files Device Initialization Configuration PinsBus Mode Detection Bus Width DetectionBus Clock Usage Family Specific ConsiderationsElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Functional Simulation Cadence IUSVerilog Mentor Graphics ModelSimFunctional Simulation Install Path/verilog/example/funcsim Mentor Graphics ModelSimTo run the simulation, type the following do modelsim.do Synthesizing a Design Synplicity SynplifySynthesizing a Design 2Main Project WindowSynplicity Synplify 3Files to Add Virtex Library5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window Exemplar LeonardoSpectrum 15Options for Implementation DeviceXilinx XST Xilinx XSTSynthesizing a Design Implementing a Design ISE FoundationImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim