Xilinx PCI-X v5.1 Installing Your License File, Full License, Direct Download, Licensing the Core

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Chapter 2: Licensing the Core

Full License

The Full license is provided when you purchase the core, and provides full access to all core functionality both in simulation and in hardware, including:

•Gate-level functional simulation support.

•Back annotated gate-level simulation support.

•Full implementation support including place and route and bitstream generation.

•Full functionality in the programmed device with no time-outs.

Obtaining a Full License

To obtain a Full license, you must purchase the core. After purchase, a full license can be downloaded from the product lounge. To create and download a license file for use with the CORE Generator software, do the following:

1.After purchase, you will receive a letter containing a serial number, which is used to register for access to the lounge; a secured area of the product page.

Go to www.xilinx.com/pci/index.htm and choose the appropriate link to gain access.

2.From the product page, click Register to request access to the lounge. Xilinx will review your access request and typically grants access to the lounge in 48 hours. (Contact Xilinx Customer Service if you need faster turnaround.)

3.After you receive confirmation of lounge access, click Access Lounge from the product page and log in.

4.From the lounge, a link at the top of the initial page allows you to generate a license. Click this link and follow the instructions to fill out the license request form; then click Submit to generate the license. An e-mail containing license and installation instructions will be sent to you immediately.

Direct Download

A CORE Generator license is not required when performing a direct download of the

Initiator/Target core for PCI-X core.

Installing Your License File

After selecting a license option, an email will be sent to you that includes instructions for installing your license file. In addition, information about advanced licensing options and technical support is provided.

16	www.xilinx.com	PCI-X v5.1 165 Getting Started Guide
		UG158 March 24, 2008

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Contents LogiCORE IP Initiator/Target v5.1 for PCI-X UG158 March 24PCI-X v5.1 165 Getting Started Guide UG158 March 24 Version RevisionUg000preface.fm to Guide Version Revision Table of Contents Implementing a Design Schedule of Figures 8Options for Implementation Options/ConstraintsPCI-X v5.1 165 Getting Started Guide Guide Contents About This GuideConventions TypographicalPreface About This Guide Convention Meaning or Use ExampleOnline Document ConventionsPreface About This Guide System Requirements Getting StartedAbout the Example Design Additional Documentation Technical SupportFeedback Core Interface for PCI-XLicensing the Core Before you BeginLicensing Options Full System Hardware EvaluationInstalling Your License File Full LicenseDirect Download Licensing the CoreFamily Specific Considerations Design SupportSimulation Virtex-4 Devices Wrapper Files Configuration Pins Bus Mode DetectionDevice Initialization Bus Width DetectionBus Clock Usage Family Specific ConsiderationsElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Functional Simulation Cadence IUSVerilog Mentor Graphics ModelSimFunctional Simulation Install Path/verilog/example/funcsim Mentor Graphics ModelSimTo run the simulation, type the following do modelsim.do Synthesizing a Design Synplicity SynplifySynthesizing a Design 2Main Project WindowSynplicity Synplify 3Files to Add Virtex Library5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window Exemplar LeonardoSpectrum 15Options for Implementation DeviceXilinx XST Xilinx XSTSynthesizing a Design Implementing a Design ISE FoundationImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim