Xilinx PCI-X v5.1 manual Simulation

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Chapter 3: Family Specific Considerations

Table 3-1:Device and Interface Selection

 

 

Wrapper File

 

Supported Device

Bus Type

Simulation

Constraints File

 

 

Model

 

 

 

 

 

2VP7-FF672-6C/I

66 MHz PCI-X

pcix_lc_64x

2vp7ff672_64x.ucf

 

3.3V 64-bit

pcix_core

 

 

 

 

 

2VP7-FF672-6C/I

100 MHz PCI-X

pcix_lc_64xf

2vp7ff672_64xf.ucf

 

3.3V 64-bit

pcix_fast

 

 

 

 

 

2VP7-FF672-6C/I

133 MHz PCI-X

pcix_lc_64xf

2vp7ff672_64xf.ucf

 

3.3V 64-bit

pcix_fast

 

 

 

 

 

2VP7-FF672-6C/I

33 MHz PCI

pcix_lc_64s

2vp7ff672_64s.ucf

 

66 MHz PCI-X

pcix_core

 

 

3.3V 64-bit

 

 

 

 

 

 

2VP20-FF1152-6C/I

33 MHz PCI

pcix_lc_64n

2vp20ff1152_64n.ucf

 

3.3V 64-bit

pcix_core

 

 

 

 

 

2VP20-FF1152-6C/I

66 MHz PCI-X

pcix_lc_64x

2vp20ff1152_64x.ucf

 

3.3V 64-bit

pcix_core

 

 

 

 

 

2VP20-FF1152-6C/I

100 MHz PCI-X

pcix_lc_64xf

2vp20ff1152_64xf.ucf

 

3.3V 64-bit

pcix_fast

 

 

 

 

 

2VP20-FF1152-6C/I

133 MHz PCI-X

pcix_lc_64xf

2vp20ff1152_64xf.ucf

 

3.3V 64-bit

pcix_fast

 

 

 

 

 

2VP20-FF1152-6C/I

33 MHz PCI

pcix_lc_64s

2vp20ff1152_64s.ucf

 

66 MHz PCI-X

pcix_core

 

 

3.3V 64-bit

 

 

 

 

 

 

2VP30-FF1152-6C/I

33 MHz PCI

pcix_lc_64n

2vp30ff1152_64n.ucf

 

3.3V 64-bit

pcix_core

 

 

 

 

 

2VP30-FF1152-6C/I

66 MHz PCI-X

pcix_lc_64x

2vp30ff1152_64x.ucf

 

3.3V 64-bit

pcix_core

 

 

 

 

 

2VP30-FF1152-6C/I

100 MHz PCI-X

pcix_lc_64xf

2vp30ff1152_64xf.ucf

 

3.3V 64-bit

pcix_fast

 

 

 

 

 

2VP30-FF1152-6C/I

133 MHz PCI-X

pcix_lc_64xf

2vp30ff1152_64xf.ucf

 

3.3V 64-bit

pcix_fast

 

 

 

 

 

2VP30-FF1152-6C/I

33 MHz PCI

pcix_lc_64s

2vp30ff1152_64s.ucf

 

66 MHz PCI-X

pcix_core

 

 

3.3V 64-bit

 

 

 

 

 

 

2VP40-FF1152-6C/I

33 MHz PCI

pcix_lc_64n

2vp40ff1152_64n.ucf

 

3.3V 64-bit

pcix_core

 

 

 

 

 

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PCI-X v5.1 165 Getting Started Guide

 

 

UG158 March 24, 2008

Image 18
Contents LogiCORE IP Initiator/Target v5.1 for PCI-X UG158 March 24PCI-X v5.1 165 Getting Started Guide UG158 March 24 Version RevisionUg000preface.fm to Guide Version Revision Table of Contents Implementing a Design Schedule of Figures 8Options for Implementation Options/ConstraintsPCI-X v5.1 165 Getting Started Guide Guide Contents About This GuidePreface About This Guide ConventionsTypographical Convention Meaning or Use ExampleOnline Document ConventionsPreface About This Guide Getting Started System RequirementsAbout the Example Design Feedback Additional DocumentationTechnical Support Core Interface for PCI-XLicensing Options Licensing the CoreBefore you Begin Full System Hardware EvaluationDirect Download Installing Your License FileFull License Licensing the CoreFamily Specific Considerations Design SupportSimulation Virtex-4 Devices Wrapper Files Device Initialization Configuration PinsBus Mode Detection Bus Width DetectionBus Clock Usage Family Specific ConsiderationsElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Functional Simulation Cadence IUSMentor Graphics ModelSim VerilogFunctional Simulation Install Path/verilog/example/funcsim Mentor Graphics ModelSimTo run the simulation, type the following do modelsim.do Synthesizing a Design Synplicity SynplifySynthesizing a Design 2Main Project WindowSynplicity Synplify 3Files to Add Virtex Library5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window Exemplar LeonardoSpectrum 15Options for Implementation DeviceXilinx XST Xilinx XSTSynthesizing a Design Implementing a Design ISE FoundationImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim