Xilinx PCI-X v5.1 manual 12Files to Add LogiCORE Files

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Chapter 5: Synthesizing a Design

The next files are located in:

<Install Path>/vhdl/src/xpci

6.Navigate to the xpci directory (Figure 5-12), select the simulation model and the wrapper files (pcix_core.vhd and pcix_lc.vhd), and click Add to move these files into the Files To Add list. (Ctrl + click to select multiple files.)

Figure 5-12:Files to Add (LogiCORE Files)

The final set of design files (the user application) is located in:

<Install Path>/vhdl/example/source

7.Navigate to the source directory (Figure 5-13), select the cfg_test_s.vhd, pcix_top.vhd, and userapp.vhd, then click Add.

Figure 5-13:Files to Add (User Application)

38	www.xilinx.com	PCI-X v5.1 165 Getting Started Guide
		UG158 March 24, 2008

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Contents LogiCORE IP Initiator/Target v5.1 for PCI-X UG158 March 24PCI-X v5.1 165 Getting Started Guide UG158 March 24 Version RevisionUg000preface.fm to Guide Version Revision Table of Contents Implementing a Design Schedule of Figures 8Options for Implementation Options/ConstraintsPCI-X v5.1 165 Getting Started Guide Guide Contents About This GuidePreface About This Guide ConventionsTypographical Convention Meaning or Use ExampleOnline Document ConventionsPreface About This Guide About the Example Design Getting StartedSystem Requirements Feedback Additional DocumentationTechnical Support Core Interface for PCI-XLicensing Options Licensing the CoreBefore you Begin Full System Hardware EvaluationDirect Download Installing Your License FileFull License Licensing the CoreFamily Specific Considerations Design SupportSimulation Virtex-4 Devices Wrapper Files Device Initialization Configuration PinsBus Mode Detection Bus Width DetectionBus Clock Usage Family Specific ConsiderationsElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Functional Simulation Cadence IUSFunctional Simulation Mentor Graphics ModelSimVerilog Install Path/verilog/example/funcsim Mentor Graphics ModelSimTo run the simulation, type the following do modelsim.do Synthesizing a Design Synplicity SynplifySynthesizing a Design 2Main Project WindowSynplicity Synplify 3Files to Add Virtex Library5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window Exemplar LeonardoSpectrum 15Options for Implementation DeviceXilinx XST Xilinx XSTSynthesizing a Design Implementing a Design ISE FoundationImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim