Xilinx PCI-X v5.1 manual Synthesizing a Design, Synplicity Synplify

Page 31

R

Chapter 5

Synthesizing a Design

This chapter describes the use of supported synthesis tools using the Userapp example design for step-by-step instructions and illustrations. If you are using a design with reference clocks, substitute pcix_top with pcix_top_r and test_tb with test_tb_r.

Supported synthesis tools include

•Synplicity Synplify

•Exemplar LeonardoSpectrum

•Xilinx XST

Each section in this chapter illustrates how to synthesize the example design for dual- mode operation with a single bitstream. The synthesis flow for other configurations is identical.

Synplicity Synplify

Before synthesizing a design, ensure that the Synplicity Synplify environment is properly configured.

Verilog

1.Start Synplify and choose File > New (Figure 5-1), or click the new file icon on the tool bar.

The New dialog appears.

Figure 5-1:Create a New Project

PCI-X v5.1 165 Getting Started Guide

www.xilinx.com

31

UG158 March 24, 2008

Image 31

Contents UG158 March 24 LogiCORE IP Initiator/Target v5.1 for PCI-XVersion Revision PCI-X v5.1 165 Getting Started Guide UG158 March 24Ug000preface.fm to Guide Version Revision Table of Contents Implementing a Design 8Options for Implementation Options/Constraints Schedule of FiguresPCI-X v5.1 165 Getting Started Guide About This Guide Guide ContentsConvention Meaning or Use Example ConventionsTypographical Preface About This GuideConventions Online DocumentPreface About This Guide System Requirements Getting StartedAbout the Example Design Core Interface for PCI-X Additional DocumentationTechnical Support FeedbackFull System Hardware Evaluation Licensing the CoreBefore you Begin Licensing OptionsLicensing the Core Installing Your License FileFull License Direct DownloadDesign Support Family Specific ConsiderationsSimulation Virtex-4 Devices Wrapper Files Bus Width Detection Configuration PinsBus Mode Detection Device InitializationFamily Specific Considerations Bus Clock UsageElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Cadence IUS Functional SimulationVerilog Mentor Graphics ModelSimFunctional Simulation Mentor Graphics ModelSim Install Path/verilog/example/funcsimTo run the simulation, type the following do modelsim.do Synplicity Synplify Synthesizing a Design2Main Project Window Synthesizing a Design3Files to Add Virtex Library Synplicity Synplify5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window 15Options for Implementation Device Exemplar LeonardoSpectrumXilinx XST Xilinx XSTSynthesizing a Design ISE Foundation Implementing a DesignImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim