Xilinx PCI-X v5.1 manual Family Specific Considerations, Design Support

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Chapter 3

Family Specific Considerations

This chapter provides important design information specific to the core interface targeting Virtex devices.

Design Support

Table 3-1provides a list of supported device and interface combinations, consisting of a device, a bus interface type, and two or three specific implementation files.

Table 3-1:Device and Interface Selection

Supported Device

Bus Type

Wrapper File

Simulation

Model

Constraints File

Virtex-E Devices

V300E-BG432-8C	33 MHz PCI	pcix_lc_64ne	v300ebg432_64n.ucf
	3.3V 64-bit	pcix_core

V300E-BG432-8C	66 MHz PCI-X	pcix_lc_64xe	v300ebg432_64x.ucf
	3.3V 64-bit	pcix_core

	Virtex-II Devices

2V1000-FG456-5C/I	33 MHz PCI	pcix_lc_64n	2v1000fg456_64n.ucf
	3.3V 64-bit	pcix_core

2V1000-FG456-5C/I	66 MHz PCI-X	pcix_lc_64x	2v1000fg456_64x.ucf
	3.3V 64-bit	pcix_core

2V1000-FG456-5C/I	100 MHz PCI-X	pcix_lc_64xf	2v1000fg456_64xf.ucf
	3.3V 64-bit	pcix_fast

2V1000-FG456-6C/I	133 MHz PCI-X	pcix_lc_64xf	2v1000fg456_64xf.ucf
	3.3V 64-bit	pcix_fast

2V1000-FG456-5C/I	33 MHz PCI	pcix_lc_64s	2v1000fg456_64s.ucf
	66 MHz PCI-X	pcix_core
	3.3V 64-bit

	Virtex-II Pro Devices

2VP7-FF672-6C/I

33 MHz PCI

3.3V 64-bit

pcix_lc_64n pcix_core

2vp7ff672_64n.ucf

PCI-X v5.1 165 Getting Started Guide

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UG158 March 24, 2008

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Contents UG158 March 24 LogiCORE IP Initiator/Target v5.1 for PCI-XVersion Revision PCI-X v5.1 165 Getting Started Guide UG158 March 24Ug000preface.fm to Guide Version Revision Table of Contents Implementing a Design 8Options for Implementation Options/Constraints Schedule of FiguresPCI-X v5.1 165 Getting Started Guide About This Guide Guide ContentsTypographical ConventionsPreface About This Guide Convention Meaning or Use ExampleConventions Online DocumentPreface About This Guide About the Example Design Getting StartedSystem Requirements Technical Support Additional DocumentationFeedback Core Interface for PCI-XBefore you Begin Licensing the CoreLicensing Options Full System Hardware EvaluationFull License Installing Your License FileDirect Download Licensing the CoreDesign Support Family Specific ConsiderationsSimulation Virtex-4 Devices Wrapper Files Bus Mode Detection Configuration PinsDevice Initialization Bus Width DetectionFamily Specific Considerations Bus Clock UsageElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Cadence IUS Functional SimulationFunctional Simulation Mentor Graphics ModelSimVerilog Mentor Graphics ModelSim Install Path/verilog/example/funcsimTo run the simulation, type the following do modelsim.do Synplicity Synplify Synthesizing a Design2Main Project Window Synthesizing a Design3Files to Add Virtex Library Synplicity Synplify5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window 15Options for Implementation Device Exemplar LeonardoSpectrumXilinx XST Xilinx XSTSynthesizing a Design ISE Foundation Implementing a DesignImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim