Xilinx PCI-X v5.1 manual Wrapper Files

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Chapter 3: Family Specific Considerations

Table 3-1:Device and Interface Selection

 

 

Wrapper File

 

Supported Device

Bus Type

Simulation

Constraints File

 

 

Model

 

 

 

 

 

4VLX25-FF668-10C/I

100 MHz PCI-X

pcix_lc_64x

4vlx25ff668_64xf.ucf

 

3.3V 64-bit

pcix_core

 

 

 

 

 

4VLX25-FF668-10C/I

133 MHz PCI-X

pcix_lc_64x

4vlx25ff668_64xf.ucf

 

3.3V 64-bit

pcix_core

 

 

 

 

 

4VSX35-FF668-10C/I

33 MHz PCI

pcix_lc_64.ng

4vsx35ff668_64ng.ucf

 

3.3V 64-bit

pcix_core

 

 

 

 

 

4VSX35-FF668-10C/I

66 MHz PCI-X

pcix_lc_64x

4vsx35ff668_64x.ucf

 

3.3V 64-bit

pcix_core

 

 

 

 

 

4VSX35-FF668-10C/I

100 MHz PCI-X

pcix_lc_64x

4vsx35ff668_64xf.ucf

 

3.3V 64-bit

pcix_core

 

 

 

 

 

4VSX35-FF668-10C/I

133 MHz PCI-X

pcix_lc_64x

4vsx35ff668_64xf.ucf

 

3.3V 64-bit

pcix_core

 

 

 

 

 

Wrapper Files

Wrapper files contain an instance of the core interface and its simulation model, as well as the instances of all I/O elements used by the core interface. Each wrapper file is specific to a particular implementation.

The wrapper files, located in the <Install Path>/hdl/src/wrap directory, are actually variations of the pcix_lc.hdl file located in the <Install Path>/hdl/src/xpci directory. The file in the <Install Path>/hdl/src/xpci is suitable for functional simulation in most modes. When starting a new design, copy the appropriate wrapper file from the wrap/ directory into the xpci/ directory, and rename it as pcix_lc.hdl.

The simulation models, located in the <Install Path>/hdl/src/xpci directory, contain structural simulation models of the interface. Note that there are multiple simulation models as there are multiple interface netlists. Each wrapper file instantiates a specific simulation model.

Constraints Files

The constraints files contain various constraints required for the core interface, and must always be used while processing a design. Each constraints file is specific to a particular device and interface—use the appropriate constraints file from the <Install Path>/hdl/src/ucf directory when processing designs using the Xilinx implementation tools.

Note: The example design relies on the presence of the default pcix_lc.hdl wrapper file in the xpci/ directory. If you change this file, you must also change the constraints files used in the processing scripts.

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PCI-X v5.1 165 Getting Started Guide

 

 

UG158 March 24, 2008

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Contents LogiCORE IP Initiator/Target v5.1 for PCI-X UG158 March 24PCI-X v5.1 165 Getting Started Guide UG158 March 24 Version RevisionUg000preface.fm to Guide Version Revision Table of Contents Implementing a Design Schedule of Figures 8Options for Implementation Options/ConstraintsPCI-X v5.1 165 Getting Started Guide Guide Contents About This GuideConventions TypographicalPreface About This Guide Convention Meaning or Use ExampleOnline Document ConventionsPreface About This Guide About the Example Design Getting StartedSystem Requirements Additional Documentation Technical SupportFeedback Core Interface for PCI-XLicensing the Core Before you BeginLicensing Options Full System Hardware EvaluationInstalling Your License File Full LicenseDirect Download Licensing the CoreFamily Specific Considerations Design SupportSimulation Virtex-4 Devices Wrapper Files Configuration Pins Bus Mode DetectionDevice Initialization Bus Width DetectionBus Clock Usage Family Specific ConsiderationsElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Functional Simulation Cadence IUSFunctional Simulation Mentor Graphics ModelSimVerilog Install Path/verilog/example/funcsim Mentor Graphics ModelSimTo run the simulation, type the following do modelsim.do Synthesizing a Design Synplicity SynplifySynthesizing a Design 2Main Project WindowSynplicity Synplify 3Files to Add Virtex Library5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window Exemplar LeonardoSpectrum 15Options for Implementation DeviceXilinx XST Xilinx XSTSynthesizing a Design Implementing a Design ISE FoundationImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim