Xilinx PCI-X v5.1 manual 9Create a New Project

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Chapter 5: Synthesizing a Design

15.On the Implementation Results tab, deselect Write Vendor Constraint File.

16.Click OK to return to the main project window.

17.From the main project window, click Run.

Synplify synthesizes the design and writes out an optimized EDIF file. In the lower- right corner of the window, the various stages or synthesis, such as Compiling or Mapping, are displayed.

When the process is complete, Done is displayed. Synplify may issue a number of warnings (which are expected) about instantiated I/O cells and attributes used for other synthesis tools.

VHDL

1.Start Synplify and choose File > New (Figure 5-9), or use the new file icon on the tool bar. The New dialog appears.

Figure 5-9:Create a New Project

2.Under File Type, select Project File and enter the project name (flowtest in this example) and synthesis directory:

<Install Path>/vhdl/example/synthesis

36	www.xilinx.com	PCI-X v5.1 165 Getting Started Guide
		UG158 March 24, 2008

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Contents LogiCORE IP Initiator/Target v5.1 for PCI-X UG158 March 24PCI-X v5.1 165 Getting Started Guide UG158 March 24 Version RevisionUg000preface.fm to Guide Version Revision Table of Contents Implementing a Design Schedule of Figures 8Options for Implementation Options/ConstraintsPCI-X v5.1 165 Getting Started Guide Guide Contents About This GuideConventions TypographicalPreface About This Guide Convention Meaning or Use ExampleOnline Document ConventionsPreface About This Guide Getting Started System RequirementsAbout the Example Design Additional Documentation Technical SupportFeedback Core Interface for PCI-XLicensing the Core Before you BeginLicensing Options Full System Hardware EvaluationInstalling Your License File Full LicenseDirect Download Licensing the CoreFamily Specific Considerations Design SupportSimulation Virtex-4 Devices Wrapper Files Configuration Pins Bus Mode DetectionDevice Initialization Bus Width DetectionBus Clock Usage Family Specific ConsiderationsElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Functional Simulation Cadence IUSMentor Graphics ModelSim VerilogFunctional Simulation Install Path/verilog/example/funcsim Mentor Graphics ModelSimTo run the simulation, type the following do modelsim.do Synthesizing a Design Synplicity SynplifySynthesizing a Design 2Main Project WindowSynplicity Synplify 3Files to Add Virtex Library5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window Exemplar LeonardoSpectrum 15Options for Implementation DeviceXilinx XST Xilinx XSTSynthesizing a Design Implementing a Design ISE FoundationImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim