Xilinx PCI-X v5.1 manual Xilinx XST

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Xilinx XST

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Note: if you run LeonardoSpectrum with the graphical user interface, the quick setup form cannot be used to synthesize the design. Instead, choose File > Run Script from the menu.

The end result of the synthesis step is an EDIF file that is fed into the Xilinx implementation tools during the implementation step.

In practice, the provided script file must be modified to accommodate other designs. To provide insight into the synthesis script, the major steps are presented below:

1.Various synthesis options are set through the use of environment variables. These must be present in the script, and should not be modified. The synthesis library is also loaded; this may be altered for different devices and speed grades.

2.The design is loaded by reading in the design files. At this point, the top level module is declared as the present_design. The script adds nopad attributes (with a value of FALSE) to all PCI-X bus interface signals. The I/O structures for these ports are directly instantiated in the wrapper file.

3.The optimization step is done with the -hierarchy preserve and the -chipoptions. The -hierarchy preserve option prevents LeonardoSpectrum from dissolving the design hierarchy. The -chipoption indicates that automatic I/O buffer insertion should be performed.

4.After synthesis is complete, the synthesized netlist is written out.

5.The tool may issue warnings about unused signals. These warnings are expected.

Xilinx XST

Before attempting to synthesize a design, ensure that the Xilinx XST environment is properly configured. Synthesis is supported only from the XST command line.

1.Navigate to the synthesis directory:

cd <Install Path>/hdl/example/synthesis

The synthesis directory contains a script for use with Xilinx XST; this script is called run_xst.bat for PC platforms and run_xst.sh for Unix platforms. Note that the run_xst.cmd and run_xst.prj files are common and used by both scripts.

2.If required, modify the files as required to suit your application. You may need to change the target architecture and select different wrapper and configuration files.

3.Synthesize the design by running the script.

The end result of the synthesis step is an NGC file, which is fed into the Xilinx implementation tools during the implementation step. The tool may issue warnings about unused signals; these warnings are expected.

PCI-X v5.1 165 Getting Started Guide

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UG158 March 24, 2008

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Contents UG158 March 24 LogiCORE IP Initiator/Target v5.1 for PCI-XVersion Revision PCI-X v5.1 165 Getting Started Guide UG158 March 24Ug000preface.fm to Guide Version Revision Table of Contents Implementing a Design 8Options for Implementation Options/Constraints Schedule of FiguresPCI-X v5.1 165 Getting Started Guide About This Guide Guide ContentsTypographical ConventionsPreface About This Guide Convention Meaning or Use ExampleConventions Online DocumentPreface About This Guide About the Example Design Getting StartedSystem Requirements Technical Support Additional DocumentationFeedback Core Interface for PCI-XBefore you Begin Licensing the CoreLicensing Options Full System Hardware EvaluationFull License Installing Your License FileDirect Download Licensing the CoreDesign Support Family Specific ConsiderationsSimulation Virtex-4 Devices Wrapper Files Bus Mode Detection Configuration PinsDevice Initialization Bus Width DetectionFamily Specific Considerations Bus Clock UsageElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Cadence IUS Functional SimulationFunctional Simulation Mentor Graphics ModelSimVerilog Mentor Graphics ModelSim Install Path/verilog/example/funcsimTo run the simulation, type the following do modelsim.do Synplicity Synplify Synthesizing a Design2Main Project Window Synthesizing a Design3Files to Add Virtex Library Synplicity Synplify5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window 15Options for Implementation Device Exemplar LeonardoSpectrumXilinx XST Xilinx XSTSynthesizing a Design ISE Foundation Implementing a DesignImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim
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