Xilinx PCI-X v5.1 manual Ug000preface.fm to Guide

Page 3

 

Version

Revision

 

 

 

04/04/02

2.2.1

Updated trademarks page in ug000_title.fm.

 

 

 

06/24/02

3.0

Initial Xilinx release of corporate-wide common template set, used for User Guides,

 

 

Tutorials, Release Notes, Manuals, and other lengthy, multiple-chapter documents

 

 

created by both CMP and ITP. See related documents for further information.

 

 

Descriptions for revisions prior to v3.0 have been abbreviated. For a full summary of revision

 

 

changes prior to v3.0, refer to v2.2.1 template set.

 

 

 

10/30/02

3.1

Updated spelling of RocketIO and SelectIO trademarks in ug000_title.fm per 10/09/02

 

 

broadcast email announcement. Also updated file version number and date.

 

 

 

12/06/02

3.2

Fixed all instances of old character formats in header/footer in Master pages.

 

 

 

01/20/03

3.3

Revised copyright date in ug000_title.fm to 2003. Changed all instances of “Manual” in

 

 

ug000_preface.fm to “Guide.”

 

 

 

02/06/03

3.4

Added paragraph formats GlossBulleted, GlossNumbered, and GlossNumberedCont.

 

 

 

02/25/03

3.4.1

Minor clean-ups and corrections.

 

 

 

03/25/03

3.5

• Corrected Reference Page identification problem that prevented the IX (index)

 

 

Reference page from taking control of Index formatting.

 

 

• Modified paragraph tags Level1IX through Level3IX (index entries) to provide a

 

 

more uniform appearance and enhance clarity.

 

 

• Removed <Italic> attribute from Heading2TOC special string on Reference pages.

 

 

• Changed autonumbering properties of FigureTitle and TableTitle to remove chapter

 

 

number and hyphen.

 

 

 

04/30/03

3.5.1

Updated Additional Resources table in Preface to give correct URL to data sheets index

 

 

page instead of to obsolete Programmable Logic Data Book page.

 

 

 

11/11/04

3.5.2

Added installation and licensing chapter; updated to current template.

 

 

 

12/1/04

3.6

Virtex-4 updates; addition of information to Family Specific Considerations, Chapter 3.

 

 

 

3/7/05

3.7

Updated to system 7.1i and build 5.0.95

 

 

 

5/13/05

4.0

Updated to build 5.0.100 and Xilinx tools 7.1i SP2.

 

 

 

8/31/05

5.0

Updated to build 5.0.101 and Xilinx tools 7.1i SP3.

 

 

 

9/12/05

6.0

Updated to build 5.0.102, Xilinx tools 7.1i to SP4, changed release date, removed

 

 

instruction to confirm directory structure from Core Licensing chapter.

 

 

 

1/18/06

7.0

Updated build to 5.0.105, Xilinx tools to 8.1i, release date, licensing chapter.

 

 

 

2/14/06

7.5

Advanced build to 108, added SP2 support to ISE v8.1i, updated release date.

 

 

 

7/13/06

8.0

Advanced build to 160, ISE to v8.21, release date

 

 

 

2/15/07

8.1

Advanced build to 161, release date, minor updates

 

 

 

5/17/07

9.0

Changed title and text references to PCI-X and PCI to comply with PCI-SIG trademark

 

 

guidelines. Advanced build to 162, support for IUS to v5.7.

 

 

 

8/08/07

9.1

Updated for IP1 Jade Minor release. Changed capacitor value to 10 uF to match XAPP653

 

 

recommendation.

 

 

 

www.xilinx.com

PCI-X v5.1 165 Getting Started Guide

 

UG158 March 24, 2008

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Contents UG158 March 24 LogiCORE IP Initiator/Target v5.1 for PCI-XVersion Revision PCI-X v5.1 165 Getting Started Guide UG158 March 24Ug000preface.fm to Guide Version Revision Table of Contents Implementing a Design 8Options for Implementation Options/Constraints Schedule of FiguresPCI-X v5.1 165 Getting Started Guide About This Guide Guide ContentsConvention Meaning or Use Example ConventionsTypographical Preface About This GuideConventions Online DocumentPreface About This Guide Getting Started System RequirementsAbout the Example Design Core Interface for PCI-X Additional DocumentationTechnical Support FeedbackFull System Hardware Evaluation Licensing the CoreBefore you Begin Licensing OptionsLicensing the Core Installing Your License FileFull License Direct DownloadDesign Support Family Specific ConsiderationsSimulation Virtex-4 Devices Wrapper Files Bus Width Detection Configuration PinsBus Mode Detection Device InitializationFamily Specific Considerations Bus Clock UsageElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Cadence IUS Functional SimulationMentor Graphics ModelSim VerilogFunctional Simulation Mentor Graphics ModelSim Install Path/verilog/example/funcsimTo run the simulation, type the following do modelsim.do Synplicity Synplify Synthesizing a Design2Main Project Window Synthesizing a Design3Files to Add Virtex Library Synplicity Synplify5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window 15Options for Implementation Device Exemplar LeonardoSpectrumXilinx XST Xilinx XSTSynthesizing a Design ISE Foundation Implementing a DesignImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim