Xilinx PCI-X v5.1 manual Synplicity Synplify, 3Files to Add Virtex Library

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Synplicity Synplify

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5.Navigate to the virtex.v file (Figure 5-3); then click Add to move this source file into the Files To Add list.

Figure 5-3:Files to Add (Virtex Library)

The next files are located in:

<Install Path>/verilog/src/xpci

6.Navigate to the xpci directory (Figure 5-4), select the simulation model and the wrapper files (pcix_core.v and pcix_lc.v), and click Add to move these files into the Files To Add list. (Ctrl + click to select multiple files.)

Figure 5-4:Files to Add (LogiCORE Files)

The final set of design files (the user application) is located in:

<Install Path>/verilog/example/source

PCI-X v5.1 165 Getting Started Guide

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UG158 March 24, 2008

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Contents UG158 March 24 LogiCORE IP Initiator/Target v5.1 for PCI-XVersion Revision PCI-X v5.1 165 Getting Started Guide UG158 March 24Ug000preface.fm to Guide Version Revision Table of Contents Implementing a Design 8Options for Implementation Options/Constraints Schedule of FiguresPCI-X v5.1 165 Getting Started Guide About This Guide Guide ContentsTypographical ConventionsPreface About This Guide Convention Meaning or Use ExampleConventions Online DocumentPreface About This Guide Getting Started System RequirementsAbout the Example Design Technical Support Additional DocumentationFeedback Core Interface for PCI-XBefore you Begin Licensing the CoreLicensing Options Full System Hardware EvaluationFull License Installing Your License FileDirect Download Licensing the CoreDesign Support Family Specific ConsiderationsSimulation Virtex-4 Devices Wrapper Files Bus Mode Detection Configuration PinsDevice Initialization Bus Width DetectionFamily Specific Considerations Bus Clock UsageElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Cadence IUS Functional SimulationMentor Graphics ModelSim VerilogFunctional Simulation Mentor Graphics ModelSim Install Path/verilog/example/funcsimTo run the simulation, type the following do modelsim.do Synplicity Synplify Synthesizing a Design2Main Project Window Synthesizing a Design3Files to Add Virtex Library Synplicity Synplify5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window 15Options for Implementation Device Exemplar LeonardoSpectrumXilinx XST Xilinx XSTSynthesizing a Design ISE Foundation Implementing a DesignImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim