Xilinx PCI-X v5.1 manual Implementing a Design, ISE Foundation

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Chapter 6

Implementing a Design

This chapter describes the use of supported FPGA implementation tools using the Userapp example design. If you are using a design with reference clocks, substitute pcix_top with pcix_top_r and test_tb with test_tb_r.

Supported FPGA implementation tools are included with the ISE Foundation v10.1 software.

ISE Foundation

Before implementing a design, ensure that the Xilinx environment is properly configured and that the design has been successfully synthesized.

1.Navigate to the implementation directory: cd <Install Path>/hdl/example/xilinx

This directory contains the run_xil_n, run_xil_s, and run_xil_x scripts. These call the appropriate tools to place and route the example design in one of three possible incarnations: PCI only, Dual Mode, and PCI-X only. Use the script that corresponds to the core configuration you have selected. For the default example design, the Dual Mode script should be used.

2.Inspect the appropriate script file and note the following:

♦The ngdbuild command lists both../../src/xpci and../synthesis as search directories. The xpci directory contains a netlist of the core interface, and the synthesis directory must contain the EDIF netlist generated during design synthesis.

♦The ngdbuild command also reads a user constraints file that corresponds to a desired target device and a particular version of the core interface.

♦To target a different device or to use a different version of the core interface, the constraints file must be changed to match the device and interface selection. The available selections are listed in the Chapter 3, “Family Specific Considerations.”

♦The user constraints files provided with the core interface contain constraints that guarantee pinout and timing specifications. These constraints must be used during processing.

♦Any additional constraints that pertain to the user application must be placed in this file. Before making additions to the user constraints file, back up the original so that it may be restored if necessary.

♦The map command requires no special arguments, but uses an input/output register packing option.

♦The PAR effort levels and delay cleanup iterations may be adjusted if necessary.

PCI-X v5.1 165 Getting Started Guide

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UG158 March 24, 2008

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Contents UG158 March 24 LogiCORE IP Initiator/Target v5.1 for PCI-XVersion Revision PCI-X v5.1 165 Getting Started Guide UG158 March 24Ug000preface.fm to Guide Version Revision Table of Contents Implementing a Design 8Options for Implementation Options/Constraints Schedule of FiguresPCI-X v5.1 165 Getting Started Guide About This Guide Guide ContentsConvention Meaning or Use Example ConventionsTypographical Preface About This GuideConventions Online DocumentPreface About This Guide System Requirements Getting StartedAbout the Example Design Core Interface for PCI-X Additional DocumentationTechnical Support FeedbackFull System Hardware Evaluation Licensing the CoreBefore you Begin Licensing OptionsLicensing the Core Installing Your License FileFull License Direct DownloadDesign Support Family Specific ConsiderationsSimulation Virtex-4 Devices Wrapper Files Bus Width Detection Configuration PinsBus Mode Detection Device InitializationFamily Specific Considerations Bus Clock UsageElectrical Compliance Electrical ComplianceInput Delay Buffers Generating Bitstreams Generating BitstreamsFamily Specific Considerations Cadence IUS Functional SimulationVerilog Mentor Graphics ModelSimFunctional Simulation Mentor Graphics ModelSim Install Path/verilog/example/funcsimTo run the simulation, type the following do modelsim.do Synplicity Synplify Synthesizing a Design2Main Project Window Synthesizing a Design3Files to Add Virtex Library Synplicity Synplify5Files to Add User Application 7Options for Implementation Device 9Create a New Project 10Main Project Window 12Files to Add LogiCORE Files 14Main Project Window 15Options for Implementation Device Exemplar LeonardoSpectrumXilinx XST Xilinx XSTSynthesizing a Design ISE Foundation Implementing a DesignImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim
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